Lines Matching defs:reg_val
1435 u32 reg_val;
1441 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1445 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1448 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1455 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1459 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1464 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1470 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1474 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1479 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1486 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1490 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1491 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1496 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1557 u32 reg_val;
1567 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1571 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1572 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1577 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1580 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1589 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1654 u16 reg_slice, reg_val;
1676 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1678 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1681 reg_val);
1697 u32 reg_val;
1703 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1707 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1715 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1718 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1727 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2535 u32 reg_val;
2540 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2544 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2545 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2550 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2554 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2558 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2564 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2569 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2570 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2572 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2577 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2857 u32 reg_val;
2908 ®_val);
2912 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2915 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2917 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2921 reg_val);