Lines Matching refs:hw
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
25 static int ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
30 * @hw: pointer to the hardware structure
35 static int ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
42 return ixgbe_get_i2c_ack(hw);
47 * @hw: pointer to the hardware structure
52 static int ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
60 return ixgbe_clock_out_i2c_bit(hw, false);
80 * @hw: pointer to the hardware structure
88 int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
106 ixgbe_i2c_start(hw);
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
120 ixgbe_i2c_start(hw);
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
134 if (ixgbe_clock_out_i2c_bit(hw, false))
136 ixgbe_i2c_stop(hw);
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
143 ixgbe_i2c_bus_clear(hw);
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
150 hw_dbg(hw, "I2C byte read combined error.\n");
158 * @hw: pointer to the hardware structure
166 int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
183 ixgbe_i2c_start(hw);
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
202 ixgbe_i2c_stop(hw);
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
208 ixgbe_i2c_bus_clear(hw);
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
215 hw_dbg(hw, "I2C byte write combined error.\n");
223 * @hw: pointer to hardware structure
228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
236 if (ixgbe_get_phy_id(hw))
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
249 hw->phy.type = ixgbe_phy_cu_unknown;
251 hw->phy.type = ixgbe_phy_generic;
259 * @hw: pointer to hardware structure
263 int ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
275 if (hw->phy.type != ixgbe_phy_unknown)
278 if (hw->phy.nw_mng_if_sel) {
280 hw->phy.nw_mng_if_sel);
281 if (ixgbe_probe_phy(hw, phy_addr))
288 if (ixgbe_probe_phy(hw, phy_addr)) {
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
306 * @hw: pointer to the hardware structure
313 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
318 if (hw->mac.type == ixgbe_mac_82598EB)
321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 hw_dbg(hw, "MNG_VETO bit detected.\n");
332 * @hw: pointer to hardware structure
335 static int ixgbe_get_phy_id(struct ixgbe_hw *hw)
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
345 hw->phy.id = (u32)(phy_id_high << 16);
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
395 * @hw: pointer to hardware structure
397 int ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
403 if (hw->phy.type == ixgbe_phy_unknown)
404 status = ixgbe_identify_phy_generic(hw);
406 if (status != 0 || hw->phy.type == ixgbe_phy_none)
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
414 if (ixgbe_check_reset_blocked(hw))
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
433 status = hw->phy.ops.read_reg(hw,
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
457 hw_dbg(hw, "PHY reset polling failed to complete.\n");
466 * @hw: pointer to hardware structure
473 int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
493 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
500 hw_dbg(hw, "PHY address command did not complete.\n");
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
521 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
527 hw_dbg(hw, "PHY read command didn't complete\n");
534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
544 * @hw: pointer to hardware structure
549 int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
552 u32 gssr = hw->phy.phy_semaphore_mask;
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
558 hw->mac.ops.release_swfw_sync(hw, gssr);
569 * @hw: pointer to hardware structure
574 int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
598 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
604 hw_dbg(hw, "PHY address cmd didn't complete\n");
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
632 hw_dbg(hw, "PHY write cmd didn't complete\n");
642 * @hw: pointer to hardware structure
647 int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
650 u32 gssr = hw->phy.phy_semaphore_mask;
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
656 hw->mac.ops.release_swfw_sync(hw, gssr);
664 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
668 * @hw: pointer to hardware structure
671 static int ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
682 * @hw: pointer to hardware structure
687 static int ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
701 data = ixgbe_msca_cmd(hw, cmd);
705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
709 hw->mac.ops.release_swfw_sync(hw, gssr);
715 * @hw: pointer to hardware structure
721 static int ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
734 data = ixgbe_msca_cmd(hw, cmd);
739 data = ixgbe_msca_cmd(hw, cmd);
743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
747 hw->mac.ops.release_swfw_sync(hw, gssr);
753 * @hw: pointer to hardware structure
759 static int ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
775 err = ixgbe_msca_cmd(hw, cmd);
777 hw->mac.ops.release_swfw_sync(hw, gssr);
783 * @hw: pointer to hardware structure
790 static int ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
806 err = ixgbe_msca_cmd(hw, cmd);
811 err = ixgbe_msca_cmd(hw, cmd);
814 hw->mac.ops.release_swfw_sync(hw, gssr);
827 struct ixgbe_hw *hw = &adapter->hw;
828 u32 gssr = hw->phy.phy_semaphore_mask;
830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 gssr = hw->phy.phy_semaphore_mask;
847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
861 struct ixgbe_hw *hw = &adapter->hw;
862 u32 gssr = hw->phy.phy_semaphore_mask;
864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
879 struct ixgbe_hw *hw = &adapter->hw;
880 u32 gssr = hw->phy.phy_semaphore_mask;
882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
896 struct ixgbe_hw *hw = &adapter->hw;
897 u32 gssr = hw->phy.phy_semaphore_mask;
900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 gssr = hw->phy.phy_semaphore_mask;
918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
932 struct ixgbe_hw *hw = &adapter->hw;
933 u32 gssr = hw->phy.phy_semaphore_mask;
936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 gssr = hw->phy.phy_semaphore_mask;
955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
984 * @hw: pointer to hardware structure
986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
990 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
992 struct ixgbe_adapter *adapter = hw->back;
1020 * @hw: pointer to hardware structure
1026 int ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1033 struct ixgbe_adapter *adapter = hw->back;
1038 switch (hw->device_id) {
1049 if (!ixgbe_x550em_a_has_mii(hw))
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1094 * @hw: pointer to hardware structure
1098 int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1120 if (hw->mac.type == ixgbe_mac_X550) {
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1129 if ((hw->phy.autoneg_advertised &
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1155 if (ixgbe_check_reset_blocked(hw))
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1172 * @hw: pointer to hardware structure
1176 int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1183 hw->phy.autoneg_advertised = 0;
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1204 if (hw->phy.ops.setup_link)
1205 hw->phy.ops.setup_link(hw);
1212 * @hw: pointer to hardware structure
1217 static int ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1234 switch (hw->mac.type) {
1236 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1241 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1252 * @hw: pointer to hardware structure
1256 int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1263 if (!hw->phy.speeds_supported)
1264 status = ixgbe_get_copper_speeds_supported(hw);
1266 *speed = hw->phy.speeds_supported;
1272 * @hw: pointer to hardware structure
1279 int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1300 status = hw->phy.ops.read_reg(hw,
1322 * @hw: pointer to hardware structure
1329 int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1335 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1339 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1344 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1347 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1354 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1359 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1362 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1369 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1375 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1378 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1384 if (ixgbe_check_reset_blocked(hw))
1388 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1393 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1400 * @hw: pointer to hardware structure
1402 int ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1412 if (ixgbe_check_reset_blocked(hw))
1415 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1418 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1422 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1430 hw_dbg(hw, "PHY reset did not complete.\n");
1435 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1440 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1446 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1454 hw_dbg(hw, "DELAY: %d MS\n", edata);
1458 hw_dbg(hw, "DATA:\n");
1460 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1465 ret_val = hw->eeprom.ops.read(hw, data_offset,
1469 hw->phy.ops.write_reg(hw, phy_offset,
1471 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1479 hw_dbg(hw, "CONTROL:\n");
1481 hw_dbg(hw, "EOL\n");
1484 hw_dbg(hw, "SOL\n");
1486 hw_dbg(hw, "Bad control value\n");
1491 hw_dbg(hw, "Bad control type\n");
1499 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1505 * @hw: pointer to hardware structure
1509 int ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1511 switch (hw->mac.ops.get_media_type(hw)) {
1513 return ixgbe_identify_sfp_module_generic(hw);
1515 return ixgbe_identify_qsfp_module_generic(hw);
1517 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1526 * @hw: pointer to hardware structure
1530 int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1532 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1533 struct ixgbe_adapter *adapter = hw->back;
1545 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1546 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1551 hw->mac.ops.set_lan_id(hw);
1553 status = hw->phy.ops.read_i2c_eeprom(hw,
1561 hw->phy.type = ixgbe_phy_sfp_unsupported;
1564 status = hw->phy.ops.read_i2c_eeprom(hw,
1571 status = hw->phy.ops.read_i2c_eeprom(hw,
1577 status = hw->phy.ops.read_i2c_eeprom(hw,
1583 status = hw->phy.ops.read_i2c_eeprom(hw,
1605 if (hw->mac.type == ixgbe_mac_82598EB) {
1607 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1609 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1611 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1613 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1616 if (hw->bus.lan_id == 0)
1617 hw->phy.sfp_type =
1620 hw->phy.sfp_type =
1623 hw->phy.ops.read_i2c_eeprom(
1624 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1628 if (hw->bus.lan_id == 0)
1629 hw->phy.sfp_type =
1632 hw->phy.sfp_type =
1635 hw->phy.sfp_type =
1641 if (hw->bus.lan_id == 0)
1642 hw->phy.sfp_type =
1645 hw->phy.sfp_type =
1648 if (hw->bus.lan_id == 0)
1649 hw->phy.sfp_type =
1652 hw->phy.sfp_type =
1655 if (hw->bus.lan_id == 0)
1656 hw->phy.sfp_type =
1659 hw->phy.sfp_type =
1662 if (hw->bus.lan_id == 0)
1663 hw->phy.sfp_type =
1666 hw->phy.sfp_type =
1674 if (hw->bus.lan_id == 0)
1675 hw->phy.sfp_type =
1678 hw->phy.sfp_type =
1681 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1685 if (hw->phy.sfp_type != stored_sfp_type)
1686 hw->phy.sfp_setup_needed = true;
1689 hw->phy.multispeed_fiber = false;
1694 hw->phy.multispeed_fiber = true;
1697 if (hw->phy.type != ixgbe_phy_nl) {
1698 hw->phy.id = identifier;
1699 status = hw->phy.ops.read_i2c_eeprom(hw,
1706 status = hw->phy.ops.read_i2c_eeprom(hw,
1713 status = hw->phy.ops.read_i2c_eeprom(hw,
1728 hw->phy.type =
1733 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1735 hw->phy.type = ixgbe_phy_sfp_ftl;
1738 hw->phy.type = ixgbe_phy_sfp_avago;
1741 hw->phy.type = ixgbe_phy_sfp_intel;
1745 hw->phy.type =
1748 hw->phy.type =
1751 hw->phy.type = ixgbe_phy_sfp_unknown;
1763 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1764 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1767 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1768 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1769 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1770 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1771 hw->phy.type = ixgbe_phy_sfp_unsupported;
1776 if (hw->mac.type == ixgbe_mac_82598EB)
1779 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1781 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1782 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1783 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1784 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1785 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1786 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1787 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1788 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1790 if (hw->phy.type == ixgbe_phy_sfp_intel)
1792 if (hw->allow_unsupported_sfp) {
1796 hw_dbg(hw, "SFP+ module not supported\n");
1797 hw->phy.type = ixgbe_phy_sfp_unsupported;
1803 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1804 if (hw->phy.type != ixgbe_phy_nl) {
1805 hw->phy.id = 0;
1806 hw->phy.type = ixgbe_phy_unknown;
1813 * @hw: pointer to hardware structure
1817 static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1819 struct ixgbe_adapter *adapter = hw->back;
1822 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1833 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1834 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1839 hw->mac.ops.set_lan_id(hw);
1841 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1848 hw->phy.type = ixgbe_phy_sfp_unsupported;
1852 hw->phy.id = identifier;
1854 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1860 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1867 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1868 if (hw->bus.lan_id == 0)
1869 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1871 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1874 if (hw->bus.lan_id == 0)
1875 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1877 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1886 hw->phy.ops.read_i2c_eeprom(hw,
1890 hw->phy.ops.read_i2c_eeprom(hw,
1894 hw->phy.ops.read_i2c_eeprom(hw,
1907 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1908 if (hw->bus.lan_id == 0)
1909 hw->phy.sfp_type =
1912 hw->phy.sfp_type =
1916 hw->phy.type = ixgbe_phy_sfp_unsupported;
1921 if (hw->phy.sfp_type != stored_sfp_type)
1922 hw->phy.sfp_setup_needed = true;
1925 hw->phy.multispeed_fiber = false;
1930 hw->phy.multispeed_fiber = true;
1935 status = hw->phy.ops.read_i2c_eeprom(hw,
1942 status = hw->phy.ops.read_i2c_eeprom(hw,
1949 status = hw->phy.ops.read_i2c_eeprom(hw,
1962 hw->phy.type = ixgbe_phy_qsfp_intel;
1964 hw->phy.type = ixgbe_phy_qsfp_unknown;
1966 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1969 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1971 if (hw->allow_unsupported_sfp) {
1975 hw_dbg(hw, "QSFP module not supported\n");
1976 hw->phy.type = ixgbe_phy_sfp_unsupported;
1984 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1985 hw->phy.id = 0;
1986 hw->phy.type = ixgbe_phy_unknown;
1993 * @hw: pointer to hardware structure
2000 int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
2005 u16 sfp_type = hw->phy.sfp_type;
2007 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
2010 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2013 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
2014 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
2035 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2036 hw_err(hw, "eeprom read at %d failed\n",
2051 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2057 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2060 hw_dbg(hw, "SFP+ module not supported\n");
2067 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2073 hw_dbg(hw, "No matching SFP+ module found\n");
2080 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2086 * @hw: pointer to hardware structure
2092 int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2095 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2102 * @hw: pointer to hardware structure
2108 int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2111 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2118 * @hw: pointer to hardware structure
2124 int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2127 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2134 * @hw: pointer to hardware structure
2138 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2142 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2149 * @hw: pointer to hardware structure
2158 static int ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2161 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2167 if (hw->mac.type >= ixgbe_mac_X550)
2169 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2175 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2178 ixgbe_i2c_start(hw);
2181 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2185 status = ixgbe_get_i2c_ack(hw);
2189 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2193 status = ixgbe_get_i2c_ack(hw);
2197 ixgbe_i2c_start(hw);
2200 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2204 status = ixgbe_get_i2c_ack(hw);
2208 status = ixgbe_clock_in_i2c_byte(hw, data);
2212 status = ixgbe_clock_out_i2c_bit(hw, nack);
2216 ixgbe_i2c_stop(hw);
2218 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2222 ixgbe_i2c_bus_clear(hw);
2224 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2229 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2231 hw_dbg(hw, "I2C byte read error.\n");
2240 * @hw: pointer to hardware structure
2248 int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2251 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2257 * @hw: pointer to hardware structure
2265 int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2268 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2274 * @hw: pointer to hardware structure
2283 static int ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2286 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2291 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2295 ixgbe_i2c_start(hw);
2297 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2301 status = ixgbe_get_i2c_ack(hw);
2305 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2309 status = ixgbe_get_i2c_ack(hw);
2313 status = ixgbe_clock_out_i2c_byte(hw, data);
2317 status = ixgbe_get_i2c_ack(hw);
2321 ixgbe_i2c_stop(hw);
2323 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2327 ixgbe_i2c_bus_clear(hw);
2330 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2332 hw_dbg(hw, "I2C byte write error.\n");
2336 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2343 * @hw: pointer to hardware structure
2351 int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2354 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2360 * @hw: pointer to hardware structure
2368 int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2371 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2377 * @hw: pointer to hardware structure
2382 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2384 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2386 i2cctl |= IXGBE_I2C_BB_EN(hw);
2389 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2390 ixgbe_raise_i2c_clk(hw, &i2cctl);
2395 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2400 ixgbe_lower_i2c_clk(hw, &i2cctl);
2409 * @hw: pointer to hardware structure
2415 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2417 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2418 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2419 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2420 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2423 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2424 ixgbe_raise_i2c_clk(hw, &i2cctl);
2429 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2437 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2438 IXGBE_WRITE_FLUSH(hw);
2444 * @hw: pointer to hardware structure
2449 static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2456 ixgbe_clock_in_i2c_bit(hw, &bit);
2465 * @hw: pointer to hardware structure
2470 static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2479 status = ixgbe_clock_out_i2c_bit(hw, bit);
2486 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2487 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2488 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2490 IXGBE_WRITE_FLUSH(hw);
2497 * @hw: pointer to hardware structure
2501 static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2503 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2504 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2511 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2514 IXGBE_WRITE_FLUSH(hw);
2516 ixgbe_raise_i2c_clk(hw, &i2cctl);
2524 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2525 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2533 hw_dbg(hw, "I2C ack was not received.\n");
2537 ixgbe_lower_i2c_clk(hw, &i2cctl);
2547 * @hw: pointer to hardware structure
2552 static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2555 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2558 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2560 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2561 IXGBE_WRITE_FLUSH(hw);
2563 ixgbe_raise_i2c_clk(hw, &i2cctl);
2568 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2569 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2571 ixgbe_lower_i2c_clk(hw, &i2cctl);
2581 * @hw: pointer to hardware structure
2586 static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2588 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2591 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2593 ixgbe_raise_i2c_clk(hw, &i2cctl);
2598 ixgbe_lower_i2c_clk(hw, &i2cctl);
2605 hw_dbg(hw, "I2C data was not set to %X\n", data);
2613 * @hw: pointer to hardware structure
2619 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2621 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2628 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2632 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2633 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2634 IXGBE_WRITE_FLUSH(hw);
2638 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2639 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2646 * @hw: pointer to hardware structure
2652 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2655 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2656 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2658 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2659 IXGBE_WRITE_FLUSH(hw);
2667 * @hw: pointer to hardware structure
2674 static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2676 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2679 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2681 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2684 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2685 IXGBE_WRITE_FLUSH(hw);
2694 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2695 IXGBE_WRITE_FLUSH(hw);
2699 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2700 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2701 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2710 * @hw: pointer to hardware structure
2716 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2718 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2722 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2723 IXGBE_WRITE_FLUSH(hw);
2727 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2734 * @hw: pointer to hardware structure
2739 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2744 ixgbe_i2c_start(hw);
2745 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2747 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2750 ixgbe_raise_i2c_clk(hw, &i2cctl);
2755 ixgbe_lower_i2c_clk(hw, &i2cctl);
2761 ixgbe_i2c_start(hw);
2764 ixgbe_i2c_stop(hw);
2769 * @hw: pointer to hardware structure
2775 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2780 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2784 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2793 * @hw: pointer to hardware structure
2796 int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2802 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2805 if (!on && ixgbe_mng_present(hw))
2808 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2815 if (ixgbe_check_reset_blocked(hw))
2820 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);