intel/ixgbe/ixgbe_phy.c

552 	u32 gssr = hw->phy.phy_semaphore_mask;
555 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
558 		hw->mac.ops.release_swfw_sync(hw, gssr);
650 	u32 gssr = hw->phy.phy_semaphore_mask;
653 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
656 		hw->mac.ops.release_swfw_sync(hw, gssr);
681  *  ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
685  *  @gssr: semaphore flags to acquire
688 					  int regnum, u32 gssr)
693 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
709 	hw->mac.ops.release_swfw_sync(hw, gssr);
714  *  ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
719  *  @gssr: semaphore flags to acquire
722 					  int devad, int regnum, u32 gssr)
727 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
747 	hw->mac.ops.release_swfw_sync(hw, gssr);
752  *  ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
757  *  @gssr: semaphore flags to acquire
760 					   int regnum, u16 val, u32 gssr)
765 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
777 	hw->mac.ops.release_swfw_sync(hw, gssr);
782  *  ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
788  *  @gssr: semaphore flags to acquire
792 					   u32 gssr)
797 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
814 	hw->mac.ops.release_swfw_sync(hw, gssr);
828 	u32 gssr = hw->phy.phy_semaphore_mask;
830 	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
845 	u32 gssr = hw->phy.phy_semaphore_mask;
847 	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
862 	u32 gssr = hw->phy.phy_semaphore_mask;
864 	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
880 	u32 gssr = hw->phy.phy_semaphore_mask;
883 					       gssr);
897 	u32 gssr = hw->phy.phy_semaphore_mask;
899 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
900 	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
915 	u32 gssr = hw->phy.phy_semaphore_mask;
917 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
918 	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
933 	u32 gssr = hw->phy.phy_semaphore_mask;
935 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
936 	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
952 	u32 gssr = hw->phy.phy_semaphore_mask;
954 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
956 					       gssr);