intel/ixgbe/ixgbe_lib.c

38 		/* If we are greater than indices move to next pool */
49 		/* If we are greater than indices move to next pool */
65 	if (fcoe->indices) {
69 		reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
77 		reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
158 	rss_i = adapter->ring_feature[RING_F_RSS].indices;
206 		/* If we are greater than indices move to next pool */
207 		if ((reg_idx & ~vmdq->mask) >= rss->indices) {
230 		/* If we are greater than indices move to next pool */
231 		if ((reg_idx & rss->mask) >= rss->indices)
368 	adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
375 	adapter->ring_feature[RING_F_RSS].indices = 1;
399 			fcoe->indices = fcoe_i;
407 			fcoe->indices = 1;
412 			fcoe->indices = 0;
455 	/* set RSS mask and indices */
458 	f->indices = rss_i;
466 	 * by feature specific indices and offset. Here we map FCoE
467 	 * indices onto the DCB queue pairs allowing FCoE to own
474 		f->indices = min_t(u16, rss_i, f->limit);
544 	adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
548 	adapter->ring_feature[RING_F_RSS].indices = rss_i;
565 	 * FCoE indices to the total ring count.
577 			fcoe->indices = fcoe_i;
583 			/* limit indices to rss_i if MSI-X is disabled */
588 			fcoe->indices = min_t(u16, fcoe_i, fcoe->limit);
589 			fcoe->offset = fcoe_i - fcoe->indices;
633 	f->indices = rss_i;
651 		rss_i = f->indices = f->limit;
676 		/* limit indices to rss_i if MSI-X is disabled */
681 		f->indices = min_t(u16, fcoe_i, f->limit);
682 		f->offset = fcoe_i - f->indices;
850 		u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
988 			    (rxr_idx < f->offset + f->indices))