intel/igc/igc_main.c

4053  * igc_write_ivar - configure ivar for given MSI-X vector
4055  * @msix_vector: vector number we are allocating to a given ring
4071 	/* write vector and valid bit */
4123 	int i, vector = 0;
4128 	/* set vector for other causes, i.e. link changes */
4139 		adapter->eims_other = BIT(vector);
4140 		tmp = (vector++ | IGC_IVAR_VALID) << 8;
4152 		igc_assign_vector(adapter->q_vector[i], vector++);
4202 		int vector = 0, i;
4204 		synchronize_irq(adapter->msix_entries[vector++].vector);
4207 			synchronize_irq(adapter->msix_entries[vector++].vector);
4242  * igc_reset_q_vector - Reset config for interrupt vector
4244  * @v_idx: Index of vector to be reset
4269  * igc_free_q_vector - Free memory allocated for specific interrupt vector
4271  * @v_idx: Index of vector to be freed
4281 	/* igc_get_stats64() might access the rings on this vector,
4480 	/* start with one vector for every Rx queue */
4490 	/* add 1 vector for link status interrupts */
4694  * igc_alloc_q_vector - Allocate memory for a single interrupt vector
4697  * @v_idx: index of vector in adapter struct
4714 	/* igc only supports 1 Tx and/or 1 Rx queue per vector */
4749 		/* rx or rx/tx vector */
4753 		/* tx only vector */
5537 	int i = 0, err = 0, vector = 0, free_vector = 0;
5540 	err = request_irq(adapter->msix_entries[vector].vector,
5554 		vector++;
5556 		q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
5570 		err = request_irq(adapter->msix_entries[vector].vector,
5582 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
5584 	vector--;
5585 	for (i = 0; i < vector; i++) {
5586 		free_irq(adapter->msix_entries[free_vector++].vector,
5916 		int vector = 0, i;
5918 		free_irq(adapter->msix_entries[vector++].vector, adapter);
5921 			free_irq(adapter->msix_entries[vector++].vector,