intel/igb/igb_main.c

726  *  igb_write_ivar - configure ivar for given MSI-X vector
728  *  @msix_vector: vector number we are allocating to a given ring
745 	/* write vector and valid bit */
769 		 * or more queues to a vector, we write the appropriate bits
770 		 * into the MSIXBM register for that vector.
840 	int i, vector = 0;
845 	/* set vector for other causes, i.e. link changes */
859 		array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
878 		adapter->eims_other = BIT(vector);
879 		tmp = (vector++ | E1000_IVAR_VALID) << 8;
891 		igb_assign_vector(adapter->q_vector[i], vector++);
907 	int i, err = 0, vector = 0, free_vector = 0;
909 	err = request_irq(adapter->msix_entries[vector].vector,
923 		vector++;
925 		q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
939 		err = request_irq(adapter->msix_entries[vector].vector,
951 	free_irq(adapter->msix_entries[free_vector++].vector, adapter);
953 	vector--;
954 	for (i = 0; i < vector; i++) {
955 		free_irq(adapter->msix_entries[free_vector++].vector,
963  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
965  *  @v_idx: Index of vector to be freed
975 	/* igb_get_stats64() might access the rings on this vector,
983  *  igb_reset_q_vector - Reset config for interrupt vector
985  *  @v_idx: Index of vector to be reset
1082 	/* start with one vector for every Rx queue */
1092 	/* add 1 vector for link status interrupts */
1145  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1148  *  @v_idx: index of vector in adapter struct
1166 	/* igb only supports 1 Tx and/or 1 Rx queue per vector */
1209 		/* rx or rx/tx vector */
1213 		/* tx only vector */
1434 		int vector = 0, i;
1436 		free_irq(adapter->msix_entries[vector++].vector, adapter);
1439 			free_irq(adapter->msix_entries[vector++].vector,
1474 			synchronize_irq(adapter->msix_entries[i].vector);