intel/igb/e1000_82575.c

122 	s32 ret_val;
127 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
128 	if (ret_val)
129 		return ret_val;
131 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
132 	if (ret_val)
133 		return ret_val;
139 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
140 	if (ret_val)
141 		return ret_val;
143 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
144 	if (ret_val)
145 		return ret_val;
159 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
160 		if (ret_val)
161 			return ret_val;
166 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
167 		if (ret_val)
168 			return ret_val;
181 	s32 ret_val = 0;
228 	ret_val = igb_get_phy_id_82575(hw);
229 	if (ret_val)
230 		return ret_val;
252 			ret_val = phy->ops.write_reg(hw,
255 			if (ret_val)
258 			ret_val = phy->ops.read_reg(hw,
261 			if (ret_val)
272 			ret_val = igb_initialize_M88E1512_phy(hw);
273 			if (ret_val)
277 			ret_val = igb_initialize_M88E1543_phy(hw);
278 			if (ret_val)
314 		ret_val = -E1000_ERR_PHY;
319 	return ret_val;
492 	s32 ret_val = E1000_ERR_CONFIG;
508 		ret_val = igb_read_sfp_data_byte(hw,
511 		if (ret_val == 0)
516 	if (ret_val != 0)
519 	ret_val = igb_read_sfp_data_byte(hw,
522 	if (ret_val != 0)
545 	ret_val = 0;
549 	return ret_val;
556 	s32 ret_val;
642 		ret_val = igb_set_sfp_media_type_82575(hw);
643 		if ((ret_val != 0) ||
674 	ret_val = igb_init_mac_params_82575(hw);
675 	if (ret_val)
679 	ret_val = igb_init_nvm_params_82575(hw);
683 		ret_val = igb_init_nvm_params_i210(hw);
689 	if (ret_val)
703 	ret_val = igb_init_phy_params_82575(hw);
706 	return ret_val;
763 	s32 ret_val = -E1000_ERR_PARAM;
770 	ret_val = hw->phy.ops.acquire(hw);
771 	if (ret_val)
774 	ret_val = igb_read_phy_reg_i2c(hw, offset, data);
779 	return ret_val;
794 	s32 ret_val = -E1000_ERR_PARAM;
802 	ret_val = hw->phy.ops.acquire(hw);
803 	if (ret_val)
806 	ret_val = igb_write_phy_reg_i2c(hw, offset, data);
811 	return ret_val;
824 	s32  ret_val = 0;
841 		ret_val = igb_get_phy_id(hw);
863 			ret_val = -E1000_ERR_PHY;
866 		ret_val = igb_get_phy_id(hw);
880 		ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
881 		if (ret_val == 0) {
897 		ret_val = -E1000_ERR_PHY;
900 		ret_val = igb_get_phy_id(hw);
907 	return ret_val;
919 	s32 ret_val;
930 	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
931 	if (ret_val)
934 	ret_val = igb_phy_sw_reset(hw);
935 	if (ret_val)
939 		ret_val = igb_initialize_M88E1512_phy(hw);
941 		ret_val = igb_initialize_M88E1543_phy(hw);
943 	return ret_val;
962 	s32 ret_val;
965 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
966 	if (ret_val)
971 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
973 		if (ret_val)
977 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
980 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
982 		if (ret_val)
986 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
994 			ret_val = phy->ops.read_reg(hw,
996 			if (ret_val)
1000 			ret_val = phy->ops.write_reg(hw,
1002 			if (ret_val)
1005 			ret_val = phy->ops.read_reg(hw,
1007 			if (ret_val)
1011 			ret_val = phy->ops.write_reg(hw,
1013 			if (ret_val)
1019 	return ret_val;
1119 	s32 ret_val;
1121 	ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1122 	if (ret_val)
1125 	ret_val = igb_acquire_nvm(hw);
1127 	if (ret_val)
1131 	return ret_val;
1160 	s32 ret_val = 0;
1165 			ret_val = -E1000_ERR_SWFW_SYNC;
1183 		ret_val = -E1000_ERR_SWFW_SYNC;
1193 	return ret_val;
1270 	s32 ret_val;
1273 		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1276 		ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1279 	return ret_val;
1291 	s32 ret_val;
1295 		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1308 		ret_val = igb_config_fc_after_link_up(hw);
1309 		if (ret_val)
1312 		ret_val = igb_check_for_copper_link(hw);
1315 	return ret_val;
1452 	s32 ret_val;
1457 	ret_val = igb_disable_pcie_master(hw);
1458 	if (ret_val)
1462 	ret_val = igb_set_pcie_completion_timeout(hw);
1463 	if (ret_val)
1480 	ret_val = igb_get_auto_rd_done(hw);
1481 	if (ret_val) {
1498 	ret_val = igb_check_alt_mac_addr(hw);
1500 	return ret_val;
1512 	s32 ret_val;
1517 		ret_val = igb_pll_workaround_i210(hw);
1518 		if (ret_val)
1519 			return ret_val;
1523 	ret_val = igb_id_led_init(hw);
1524 	if (ret_val) {
1547 	ret_val = igb_setup_link(hw);
1555 	return ret_val;
1569 	s32  ret_val;
1591 	ret_val = igb_setup_serdes_link_82575(hw);
1592 	if (ret_val)
1599 		ret_val = hw->phy.ops.reset(hw);
1600 		if (ret_val) {
1614 			ret_val = igb_copper_link_setup_m88_gen2(hw);
1617 			ret_val = igb_copper_link_setup_m88(hw);
1622 		ret_val = igb_copper_link_setup_igp(hw);
1625 		ret_val = igb_copper_link_setup_82580(hw);
1628 		ret_val = 0;
1631 		ret_val = -E1000_ERR_PHY;
1635 	if (ret_val)
1638 	ret_val = igb_setup_copper_link(hw);
1640 	return ret_val;
1656 	s32 ret_val = 0;
1661 		return ret_val;
1709 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1710 			if (ret_val) {
1712 				return ret_val;
1782 	return ret_val;
1841 	s32 ret_val = 0;
1847 	ret_val = igb_check_alt_mac_addr(hw);
1848 	if (ret_val)
1851 	ret_val = igb_read_mac_addr(hw);
1854 	return ret_val;
2024 	s32 ret_val = 0;
2043 	ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2045 	if (ret_val)
2050 	ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2057 	return ret_val;
2165 	s32 ret_val;
2167 	ret_val = hw->phy.ops.acquire(hw);
2168 	if (ret_val)
2171 	ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2176 	return ret_val;
2189 	s32 ret_val;
2192 	ret_val = hw->phy.ops.acquire(hw);
2193 	if (ret_val)
2196 	ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2201 	return ret_val;
2214 	s32 ret_val = 0;
2223 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2226 	if (ret_val) {
2238 	return ret_val;
2250 	s32 ret_val = 0;
2270 	ret_val = igb_disable_pcie_master(hw);
2271 	if (ret_val)
2300 	ret_val = igb_get_auto_rd_done(hw);
2301 	if (ret_val) {
2316 	ret_val = igb_reset_mdicnfg_82580(hw);
2317 	if (ret_val)
2321 	ret_val = igb_check_alt_mac_addr(hw);
2327 	return ret_val;
2342 	u16 ret_val = 0;
2345 		ret_val = e1000_82580_rxpbs_table[data];
2347 	return ret_val;
2362 	s32 ret_val = 0;
2367 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2368 		if (ret_val) {
2377 		ret_val = -E1000_ERR_NVM;
2382 	return ret_val;
2397 	s32 ret_val;
2402 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2403 		if (ret_val) {
2410 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2412 	if (ret_val)
2416 	return ret_val;
2429 	s32 ret_val = 0;
2434 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2435 	if (ret_val) {
2449 		ret_val = igb_validate_nvm_checksum_with_offset(hw,
2451 		if (ret_val != 0)
2456 	return ret_val;
2469 	s32 ret_val;
2473 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2474 	if (ret_val) {
2482 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2484 		if (ret_val) {
2492 		ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2493 		if (ret_val)
2498 	return ret_val;
2511 	s32 ret_val = 0;
2517 		ret_val = igb_validate_nvm_checksum_with_offset(hw,
2519 		if (ret_val != 0)
2524 	return ret_val;
2537 	s32 ret_val = 0;
2543 		ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2544 		if (ret_val != 0)
2549 	return ret_val;
2562 	s32 ret_val = 0;
2564 	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2565 	if (ret_val)
2566 		return ret_val;
2569 		ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2571 		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2573 	return ret_val;
2655 	s32 ret_val = 0;
2665 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2666 		if (ret_val)
2669 		ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2671 		if (ret_val)
2675 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2677 		if (ret_val)
2681 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2682 		if (ret_val)
2686 		ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2689 		if (ret_val)
2702 		ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2707 		ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2710 		if (ret_val)
2715 		ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2721 	return ret_val;
2735 	s32 ret_val = 0;
2744 	ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2747 	if (ret_val)
2754 	return ret_val;