intel/igb/e1000_82575.c

328 	struct e1000_nvm_info *nvm = &hw->nvm;
345 	nvm->word_size = BIT(size);
346 	nvm->opcode_bits = 8;
347 	nvm->delay_usec = 1;
349 	switch (nvm->override) {
351 		nvm->page_size = 32;
352 		nvm->address_bits = 16;
355 		nvm->page_size = 8;
356 		nvm->address_bits = 8;
359 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
360 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
364 	if (nvm->word_size == BIT(15))
365 		nvm->page_size = 128;
367 	nvm->type = e1000_nvm_eeprom_spi;
370 	nvm->ops.acquire = igb_acquire_nvm_82575;
371 	nvm->ops.release = igb_release_nvm_82575;
372 	nvm->ops.write = igb_write_nvm_spi;
373 	nvm->ops.validate = igb_validate_nvm_checksum;
374 	nvm->ops.update = igb_update_nvm_checksum;
375 	if (nvm->word_size < BIT(15))
376 		nvm->ops.read = igb_read_nvm_eerd;
378 		nvm->ops.read = igb_read_nvm_spi;
383 		nvm->ops.validate = igb_validate_nvm_checksum_82580;
384 		nvm->ops.update = igb_update_nvm_checksum_82580;
388 		nvm->ops.validate = igb_validate_nvm_checksum_i350;
389 		nvm->ops.update = igb_update_nvm_checksum_i350;
1709 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
2223 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2367 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2402 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2410 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2434 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2473 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2482 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2794 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2798 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2808 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2853 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2857 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2866 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);