Lines Matching refs:err
428 int err;
433 err = ice_sbq_rw_reg(hw, &msg);
434 if (err) {
435 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
436 err);
437 return err;
462 int err;
473 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low);
474 if (err) {
475 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
476 low_addr, err);
477 return err;
480 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high);
481 if (err) {
482 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
483 high_addr, err);
484 return err;
505 int err;
511 err = ice_sbq_rw_reg(hw, &msg);
512 if (err) {
513 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
514 err);
515 return err;
536 int err;
550 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
551 if (err) {
552 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
553 low_addr, err);
554 return err;
557 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
558 if (err) {
559 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
560 high_addr, err);
561 return err;
584 int err;
598 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
599 if (err) {
600 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
601 low_addr, err);
602 return err;
605 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
606 if (err) {
607 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
608 high_addr, err);
609 return err;
659 int err;
661 err = ice_fill_quad_msg_e82x(&msg, quad, offset);
662 if (err)
663 return err;
667 err = ice_sbq_rw_reg(hw, &msg);
668 if (err) {
669 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
670 err);
671 return err;
693 int err;
695 err = ice_fill_quad_msg_e82x(&msg, quad, offset);
696 if (err)
697 return err;
702 err = ice_sbq_rw_reg(hw, &msg);
703 if (err) {
704 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
705 err);
706 return err;
728 int err;
733 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);
734 if (err) {
735 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
736 err);
737 return err;
740 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);
741 if (err) {
742 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
743 err);
744 return err;
782 int err;
784 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);
785 if (err) {
786 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
787 quad, idx, err);
788 return err;
833 int err;
840 err = ice_sbq_rw_reg(hw, &cgu_msg);
841 if (err) {
842 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
843 addr, err);
844 return err;
849 return err;
865 int err;
873 err = ice_sbq_rw_reg(hw, &cgu_msg);
874 if (err) {
875 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
876 addr, err);
877 return err;
880 return err;
945 int err;
966 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
967 if (err)
968 return err;
970 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
971 if (err)
972 return err;
974 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
975 if (err)
976 return err;
989 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
990 if (err)
991 return err;
996 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
997 if (err)
998 return err;
1001 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
1002 if (err)
1003 return err;
1008 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
1009 if (err)
1010 return err;
1013 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
1014 if (err)
1015 return err;
1020 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
1021 if (err)
1022 return err;
1025 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
1026 if (err)
1027 return err;
1033 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
1034 if (err)
1035 return err;
1040 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
1041 if (err)
1042 return err;
1047 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
1048 if (err)
1049 return err;
1076 int err;
1078 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
1080 if (err)
1081 return err;
1083 /* Disable sticky lock detection so lock err reported is accurate */
1087 err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
1089 if (err)
1090 return err;
1095 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
1097 if (err)
1098 return err;
1114 int err;
1116 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
1118 if (err) {
1119 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
1120 port, err);
1121 return err;
1136 int err;
1148 err = ice_init_cgu_e82x(hw);
1149 if (err)
1150 return err;
1171 int err;
1180 err = ice_write_64b_phy_reg_e82x(hw, port,
1183 if (err)
1187 err = ice_write_64b_phy_reg_e82x(hw, port,
1190 if (err)
1197 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1198 port, err);
1200 return err;
1222 int err;
1228 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,
1230 if (err)
1233 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,
1235 if (err)
1239 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,
1241 if (err)
1244 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,
1246 if (err)
1252 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1253 port, err);
1254 return err;
1282 int err;
1284 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
1285 if (err)
1286 return err;
1304 int err;
1308 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
1310 if (err)
1317 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1318 port, err);
1320 return err;
1337 int err;
1340 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
1341 if (err) {
1342 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1343 err);
1344 return err;
1351 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
1352 if (err) {
1353 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1354 err);
1355 return err;
1380 int err;
1406 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, &val);
1407 if (err) {
1408 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n",
1409 err);
1410 return err;
1417 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
1418 if (err) {
1419 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1420 err);
1421 return err;
1426 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, &val);
1427 if (err) {
1428 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n",
1429 err);
1430 return err;
1437 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, val);
1438 if (err) {
1439 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1440 err);
1441 return err;
1465 int err;
1472 err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);
1473 if (err)
1474 return err;
1494 int err;
1496 err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);
1497 if (err)
1498 return err;
1529 int err;
1531 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes);
1532 if (err) {
1534 return err;
1595 int err;
1599 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL);
1600 if (err) {
1601 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
1602 err);
1608 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
1609 if (err) {
1610 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
1611 err);
1620 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
1621 if (err) {
1622 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
1623 err);
1677 int err;
1691 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,
1693 if (err) {
1694 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
1695 err);
1696 return err;
1702 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,
1704 if (err) {
1705 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
1706 err);
1707 return err;
1761 int err;
1763 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
1764 if (err)
1765 return err;
1787 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,
1789 if (err)
1790 return err;
1799 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,
1801 if (err)
1802 return err;
1811 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,
1813 if (err)
1814 return err;
1823 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,
1825 if (err)
1826 return err;
1835 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,
1837 if (err)
1838 return err;
1847 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,
1849 if (err)
1850 return err;
1859 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,
1861 if (err)
1862 return err;
1934 int err;
1938 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®);
1939 if (err) {
1940 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
1941 port, err);
1942 return err;
1948 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®);
1949 if (err) {
1950 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
1951 port, err);
1952 return err;
1958 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
1959 if (err)
1960 return err;
1973 err = ice_read_64b_phy_reg_e82x(hw, port,
1976 if (err)
1977 return err;
1988 err = ice_read_64b_phy_reg_e82x(hw, port,
1991 if (err)
1992 return err;
2001 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,
2003 if (err)
2004 return err;
2006 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);
2007 if (err)
2008 return err;
2036 int err;
2038 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val);
2039 if (err) {
2040 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
2041 err);
2042 return err;
2126 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,
2128 if (err) {
2129 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
2130 err);
2131 return err;
2148 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,
2150 if (err) {
2151 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
2152 err);
2153 return err;
2237 int err;
2241 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®);
2242 if (err) {
2243 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
2244 port, err);
2245 return err;
2251 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®);
2252 if (err) {
2253 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
2254 port, err);
2255 return err;
2261 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
2262 if (err)
2263 return err;
2270 err = ice_read_64b_phy_reg_e82x(hw, port,
2273 if (err)
2274 return err;
2285 err = ice_read_64b_phy_reg_e82x(hw, port,
2288 if (err)
2289 return err;
2295 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd);
2296 if (err)
2297 return err;
2311 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,
2313 if (err)
2314 return err;
2316 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);
2317 if (err)
2318 return err;
2343 int err;
2351 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
2352 if (err)
2353 return err;
2364 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
2365 if (err)
2366 return err;
2398 int err;
2405 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
2406 if (err)
2419 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);
2420 if (err)
2423 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2424 if (err)
2436 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
2437 if (err)
2451 return err;
2467 int err;
2470 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
2471 if (err)
2472 return err;
2474 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
2475 if (err)
2476 return err;
2478 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
2479 if (err)
2480 return err;
2483 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2484 if (err)
2485 return err;
2488 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2489 if (err)
2490 return err;
2494 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2495 if (err)
2496 return err;
2520 int err;
2524 err = ice_stop_phy_timer_e82x(hw, port, false);
2525 if (err)
2526 return err;
2530 err = ice_phy_cfg_uix_e82x(hw, port);
2531 if (err)
2532 return err;
2534 err = ice_phy_cfg_parpcs_e82x(hw, port);
2535 if (err)
2536 return err;
2542 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);
2543 if (err)
2544 return err;
2546 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2547 if (err)
2548 return err;
2555 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
2556 if (err)
2557 return err;
2560 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2561 if (err)
2562 return err;
2565 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2566 if (err)
2567 return err;
2570 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2571 if (err)
2572 return err;
2574 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2575 if (err)
2576 return err;
2581 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2582 if (err)
2583 return err;
2586 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
2587 if (err)
2588 return err;
2592 err = ice_sync_phy_timer_e82x(hw, port);
2593 if (err)
2594 return err;
2615 int err;
2617 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
2618 if (err) {
2619 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
2620 quad, err);
2621 return err;
2624 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
2625 if (err) {
2626 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
2627 quad, err);
2628 return err;
2653 int err;
2660 err = ice_sbq_rw_reg(hw, &msg);
2661 if (err) {
2662 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2663 err);
2664 return err;
2683 int err;
2691 err = ice_sbq_rw_reg(hw, &msg);
2692 if (err) {
2693 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2694 err);
2695 return err;
2762 int err;
2764 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
2765 if (err) {
2766 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
2767 err);
2768 return err;
2771 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
2772 if (err) {
2773 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
2774 err);
2775 return err;
2799 int err;
2802 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
2804 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
2806 if (err)
2807 return err;
2833 int err;
2835 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
2836 if (err) {
2837 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
2838 lport, idx, err);
2839 return err;
2845 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
2846 if (err) {
2847 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
2848 lport, idx, err);
2849 return err;
2852 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
2853 if (err) {
2854 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
2855 lport, idx, err);
2856 return err;
2872 int err;
2875 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
2877 if (err)
2879 err);
2881 return err;
2914 int err;
2917 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
2918 if (err) {
2919 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
2920 err);
2921 return err;
2924 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
2925 if (err) {
2926 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
2927 err);
2928 return err;
2950 int err;
2957 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
2958 if (err) {
2959 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
2960 err);
2961 return err;
2964 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
2965 if (err) {
2966 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
2967 err);
2968 return err;
2987 int err;
2993 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
2994 if (err) {
2995 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
2996 err);
2997 return err;
3000 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
3001 if (err) {
3002 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
3003 err);
3004 return err;
3021 int err;
3044 err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val);
3045 if (err) {
3046 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err);
3047 return err;
3054 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val);
3055 if (err) {
3056 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err);
3057 return err;
3224 int err;
3228 err = ice_get_pca9575_handle(hw, &handle);
3229 if (err)
3230 return err;
3325 int err;
3333 err = ice_ptp_port_cmd_e810(hw, cmd);
3336 err = ice_ptp_port_cmd_e82x(hw, cmd);
3339 err = -EOPNOTSUPP;
3342 if (err) {
3343 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
3344 cmd, err);
3345 return err;
3372 int err;
3385 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
3388 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF);
3391 err = -EOPNOTSUPP;
3394 if (err)
3395 return err;
3417 int err;
3427 err = ice_ptp_prep_phy_incval_e810(hw, incval);
3430 err = ice_ptp_prep_phy_incval_e82x(hw, incval);
3433 err = -EOPNOTSUPP;
3436 if (err)
3437 return err;
3451 int err;
3456 err = ice_ptp_write_incval(hw, incval);
3460 return err;
3479 int err;
3493 err = ice_ptp_prep_phy_adj_e810(hw, adj);
3496 err = ice_ptp_prep_phy_adj_e82x(hw, adj);
3499 err = -EOPNOTSUPP;
3502 if (err)
3503 return err;
3633 /* Clear event err indications for auxiliary pins */