Lines Matching refs:pf
35 * @pf: private board structure
44 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack)
46 if (ice_is_reset_in_progress(pf->state)) {
55 * @pf: private board structure
63 * Context: Called under pf->dplls.lock
69 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin,
79 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags,
84 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags,
94 ice_aq_str(pf->hw.adminq.sq_last_status),
115 * Context: Acquires pf->dplls.lock
129 struct ice_pf *pf = d->pf;
132 if (ice_dpll_is_reset(pf, extack))
135 mutex_lock(&pf->dplls.lock);
136 ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack);
137 mutex_unlock(&pf->dplls.lock);
153 * Context: Calls a function which acquires pf->dplls.lock
178 * Context: Calls a function which acquires pf->dplls.lock
204 * Context: Acquires pf->dplls.lock
217 struct ice_pf *pf = d->pf;
219 mutex_lock(&pf->dplls.lock);
221 mutex_unlock(&pf->dplls.lock);
237 * Context: Calls a function which acquires pf->dplls.lock
262 * Context: Calls a function which acquires pf->dplls.lock
286 * Context: Called under pf->dplls.lock
335 * Context: Called under pf->dplls.lock
373 * @pf: private board struct
382 * Context: Called under pf->dplls.lock
388 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
397 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL,
404 pin->state[pf->dplls.eec.dpll_idx] =
405 pin->pin == pf->dplls.eec.active_input ?
408 pin->state[pf->dplls.pps.dpll_idx] =
409 pin->pin == pf->dplls.pps.active_input ?
413 pin->state[pf->dplls.eec.dpll_idx] =
415 pin->state[pf->dplls.pps.dpll_idx] =
419 pin->state[pf->dplls.eec.dpll_idx] =
421 pin->state[pf->dplls.pps.dpll_idx] =
426 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx,
434 pin->state[pf->dplls.eec.dpll_idx] =
435 parent == pf->dplls.eec.dpll_idx ?
438 pin->state[pf->dplls.pps.dpll_idx] =
439 parent == pf->dplls.pps.dpll_idx ?
443 pin->state[pf->dplls.eec.dpll_idx] =
445 pin->state[pf->dplls.pps.dpll_idx] =
450 for (parent = 0; parent < pf->dplls.rclk.num_parents;
454 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p,
478 ice_aq_str(pf->hw.adminq.sq_last_status),
481 dev_err_ratelimited(ice_pf_to_dev(pf),
484 ice_aq_str(pf->hw.adminq.sq_last_status),
491 * @pf: board private structure
499 * Context: Called under pf->dplls.lock
505 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll,
511 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx,
517 ice_aq_str(pf->hw.adminq.sq_last_status),
535 * Context: Acquires pf->dplls.lock
547 struct ice_pf *pf = d->pf;
549 mutex_lock(&pf->dplls.lock);
551 mutex_unlock(&pf->dplls.lock);
565 * Context: Acquires pf->dplls.lock
575 struct ice_pf *pf = d->pf;
577 mutex_lock(&pf->dplls.lock);
579 mutex_unlock(&pf->dplls.lock);
596 * Context: Acquires pf->dplls.lock
609 struct ice_pf *pf = d->pf;
612 if (ice_dpll_is_reset(pf, extack))
615 mutex_lock(&pf->dplls.lock);
617 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type,
620 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack);
622 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack);
623 mutex_unlock(&pf->dplls.lock);
639 * Context: Calls a function which acquires pf->dplls.lock
672 * Context: Calls a function which acquires pf->dplls.lock
701 * Context: Acquires pf->dplls.lock
715 struct ice_pf *pf = d->pf;
718 if (ice_dpll_is_reset(pf, extack))
721 mutex_lock(&pf->dplls.lock);
722 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack);
730 mutex_unlock(&pf->dplls.lock);
746 * Context: Calls a function which acquires pf->dplls.lock
772 * Context: Calls a function which acquires pf->dplls.lock
798 * Context: Acquires pf->dplls.lock
810 struct ice_pf *pf = d->pf;
812 mutex_lock(&pf->dplls.lock);
814 mutex_unlock(&pf->dplls.lock);
830 * Context: Acquires pf->dplls.lock
842 struct ice_pf *pf = d->pf;
845 if (ice_dpll_is_reset(pf, extack))
848 mutex_lock(&pf->dplls.lock);
849 ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack);
850 mutex_unlock(&pf->dplls.lock);
916 * Context: Acquires pf->dplls.lock
928 struct ice_pf *pf = p->pf;
930 mutex_lock(&pf->dplls.lock);
932 mutex_unlock(&pf->dplls.lock);
950 * Context: Acquires pf->dplls.lock
964 struct ice_pf *pf = d->pf;
968 if (ice_dpll_is_reset(pf, extack))
971 mutex_lock(&pf->dplls.lock);
979 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
988 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
996 mutex_unlock(&pf->dplls.lock);
1001 ice_aq_str(pf->hw.adminq.sq_last_status),
1019 * Context: Calls a function which acquires pf->dplls.lock
1047 * Context: Calls a function which acquires pf->dplls.lock
1078 * Context: Acquires pf->dplls.lock
1089 struct ice_pf *pf = d->pf;
1091 mutex_lock(&pf->dplls.lock);
1096 mutex_unlock(&pf->dplls.lock);
1112 * Context: Acquires pf->dplls.lock
1126 struct ice_pf *pf = p->pf;
1130 if (ice_dpll_is_reset(pf, extack))
1133 mutex_lock(&pf->dplls.lock);
1134 hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1135 if (hw_idx >= pf->dplls.num_inputs)
1145 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable,
1151 ice_aq_str(pf->hw.adminq.sq_last_status),
1154 mutex_unlock(&pf->dplls.lock);
1170 * Context: Acquires pf->dplls.lock
1183 struct ice_pf *pf = p->pf;
1187 if (ice_dpll_is_reset(pf, extack))
1190 mutex_lock(&pf->dplls.lock);
1191 hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1192 if (hw_idx >= pf->dplls.num_inputs)
1195 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT,
1203 mutex_unlock(&pf->dplls.lock);
1244 * @pf: board private structure
1251 static u64 ice_generate_clock_id(struct ice_pf *pf)
1253 return pci_get_dsn(pf->pdev);
1288 * @pf: pf private structure
1294 * Context: Called by kworker under pf->dplls.lock
1300 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
1305 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
1309 dev_dbg(ice_pf_to_dev(pf),
1314 dev_err(ice_pf_to_dev(pf),
1317 ice_aq_str(pf->hw.adminq.sq_last_status));
1323 d->active_input = pf->dplls.inputs[d->input_idx].pin;
1324 p = &pf->dplls.inputs[d->input_idx];
1325 return ice_dpll_pin_state_update(pf, p,
1332 p = &pf->dplls.inputs[d->input_idx];
1337 ret = ice_dpll_pin_state_update(pf, p,
1341 p = &pf->dplls.inputs[d->prev_input_idx];
1342 ice_dpll_pin_state_update(pf, p,
1347 p = &pf->dplls.inputs[d->input_idx];
1349 ice_dpll_pin_state_update(pf, p,
1364 * Context: Holds pf->dplls.lock
1369 struct ice_pf *pf = container_of(d, struct ice_pf, dplls);
1370 struct ice_dpll *de = &pf->dplls.eec;
1371 struct ice_dpll *dp = &pf->dplls.pps;
1374 if (ice_is_reset_in_progress(pf->state))
1376 mutex_lock(&pf->dplls.lock);
1377 ret = ice_dpll_update_state(pf, de, false);
1379 ret = ice_dpll_update_state(pf, dp, false);
1385 dev_err(ice_pf_to_dev(pf),
1387 mutex_unlock(&pf->dplls.lock);
1391 mutex_unlock(&pf->dplls.lock);
1419 * @pf: board private structure
1433 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins,
1535 * @pf: board private structure
1552 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu,
1559 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id);
1582 * @pf: board private structure
1586 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf)
1588 struct ice_dpll_pin *rclk = &pf->dplls.rclk;
1589 struct ice_vsi *vsi = ice_get_main_vsi(pf);
1594 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin;
1608 * @pf: board private structure
1614 * pin with the parents it has in the info. Register pin with the pf's main vsi
1622 ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin,
1625 struct ice_vsi *vsi = ice_get_main_vsi(pf);
1629 ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF,
1630 pf->dplls.clock_id);
1633 for (i = 0; i < pf->dplls.rclk.num_parents; i++) {
1634 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin;
1639 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin,
1640 ops, &pf->dplls.rclk);
1646 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin);
1652 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin;
1653 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin,
1654 &ice_dpll_rclk_ops, &pf->dplls.rclk);
1662 * @pf: board private structure
1663 * @cgu: if cgu is controlled by this pf
1668 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu)
1670 struct ice_dpll_pin *outputs = pf->dplls.outputs;
1671 struct ice_dpll_pin *inputs = pf->dplls.inputs;
1672 int num_outputs = pf->dplls.num_outputs;
1673 int num_inputs = pf->dplls.num_inputs;
1674 struct ice_dplls *d = &pf->dplls;
1678 ice_dpll_deinit_rclk_pin(pf);
1697 * @pf: board private structure
1700 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
1707 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu)
1712 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0,
1713 pf->dplls.num_inputs,
1715 pf->dplls.eec.dpll, pf->dplls.pps.dpll);
1719 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs,
1720 pf->dplls.num_inputs,
1721 pf->dplls.num_outputs,
1723 pf->dplls.eec.dpll,
1724 pf->dplls.pps.dpll);
1728 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id;
1729 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx,
1736 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs,
1737 pf->dplls.num_outputs,
1738 &ice_dpll_output_ops, pf->dplls.pps.dpll,
1739 pf->dplls.eec.dpll);
1741 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs,
1742 &ice_dpll_input_ops, pf->dplls.pps.dpll,
1743 pf->dplls.eec.dpll);
1749 * @pf: board private structure
1757 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu)
1766 * @pf: board private structure
1779 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu,
1782 u64 clock_id = pf->dplls.clock_id;
1788 dev_err(ice_pf_to_dev(pf),
1792 d->pf = pf;
1794 ice_dpll_update_state(pf, d, true);
1807 * @pf: board private structure
1811 static void ice_dpll_deinit_worker(struct ice_pf *pf)
1813 struct ice_dplls *d = &pf->dplls;
1821 * @pf: board private structure
1825 * Context: Shall be called after pf->dplls.lock is initialized.
1830 static int ice_dpll_init_worker(struct ice_pf *pf)
1832 struct ice_dplls *d = &pf->dplls;
1837 dev_name(ice_pf_to_dev(pf)));
1849 * @pf: board private structure
1852 * Init information for directly connected pins, cache them in pf's pins
1860 ice_dpll_init_info_direct_pins(struct ice_pf *pf,
1863 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;
1865 struct ice_hw *hw = &pf->hw;
1873 pins = pf->dplls.inputs;
1874 num_pins = pf->dplls.num_inputs;
1878 pins = pf->dplls.outputs;
1879 num_pins = pf->dplls.num_outputs;
1903 pf->dplls.input_phase_adj_max;
1905 -pf->dplls.input_phase_adj_max;
1908 pf->dplls.output_phase_adj_max;
1910 -pf->dplls.output_phase_adj_max;
1916 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
1922 pins[i].pf = pf;
1930 * @pf: board private structure
1932 * Init information for rclk pin, cache them in pf->dplls.rclk.
1938 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf)
1940 struct ice_dpll_pin *pin = &pf->dplls.rclk;
1944 pin->pf = pf;
1946 return ice_dpll_pin_state_update(pf, pin,
1952 * @pf: board private structure
1962 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type)
1967 return ice_dpll_init_info_direct_pins(pf, pin_type);
1969 return ice_dpll_init_info_rclk_pin(pf);
1977 * @pf: board private structure
1981 static void ice_dpll_deinit_info(struct ice_pf *pf)
1983 kfree(pf->dplls.inputs);
1984 kfree(pf->dplls.outputs);
1985 kfree(pf->dplls.eec.input_prio);
1986 kfree(pf->dplls.pps.input_prio);
1990 * ice_dpll_init_info - prepare pf's dpll information structure
1991 * @pf: board private structure
1994 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
2000 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu)
2003 struct ice_dpll *de = &pf->dplls.eec;
2004 struct ice_dpll *dp = &pf->dplls.pps;
2005 struct ice_dplls *d = &pf->dplls;
2006 struct ice_hw *hw = &pf->hw;
2009 d->clock_id = ice_generate_clock_id(pf);
2012 dev_err(ice_pf_to_dev(pf),
2039 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT);
2051 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT);
2056 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx,
2057 &pf->dplls.rclk.num_parents);
2060 for (i = 0; i < pf->dplls.rclk.num_parents; i++)
2061 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i;
2062 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT);
2068 dev_dbg(ice_pf_to_dev(pf),
2075 dev_err(ice_pf_to_dev(pf),
2079 ice_dpll_deinit_info(pf);
2086 * @pf: board private structure
2092 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2094 void ice_dpll_deinit(struct ice_pf *pf)
2096 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU);
2098 clear_bit(ICE_FLAG_DPLL, pf->flags);
2100 ice_dpll_deinit_worker(pf);
2102 ice_dpll_deinit_pins(pf, cgu);
2103 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);
2104 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu);
2105 ice_dpll_deinit_info(pf);
2106 mutex_destroy(&pf->dplls.lock);
2111 * @pf: board private structure
2117 * Context: Initializes pf->dplls.lock mutex.
2119 void ice_dpll_init(struct ice_pf *pf)
2121 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU);
2122 struct ice_dplls *d = &pf->dplls;
2126 err = ice_dpll_init_info(pf, cgu);
2129 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC);
2132 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS);
2135 err = ice_dpll_init_pins(pf, cgu);
2139 err = ice_dpll_init_worker(pf);
2143 set_bit(ICE_FLAG_DPLL, pf->flags);
2148 ice_dpll_deinit_pins(pf, cgu);
2150 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);
2152 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu);
2154 ice_dpll_deinit_info(pf);
2157 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err);