intel/ice/ice_controlq.c

8 	(qinfo)->sq.head = prefix##_ATQH;			\
9 	(qinfo)->sq.tail = prefix##_ATQT;			\
10 	(qinfo)->sq.len = prefix##_ATQLEN;			\
11 	(qinfo)->sq.bah = prefix##_ATQBAH;			\
12 	(qinfo)->sq.bal = prefix##_ATQBAL;			\
13 	(qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M;	\
14 	(qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M;	\
15 	(qinfo)->sq.len_crit_mask = prefix##_ATQLEN_ATQCRIT_M;	\
16 	(qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M;		\
77 	if (cq->sq.len && cq->sq.len_mask && cq->sq.len_ena_mask)
78 		return (rd32(hw, cq->sq.len) & (cq->sq.len_mask |
79 						cq->sq.len_ena_mask)) ==
80 			(cq->num_sq_entries | cq->sq.len_ena_mask);
95 	cq->sq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size,
96 						 &cq->sq.desc_buf.pa,
98 	if (!cq->sq.desc_buf.va)
100 	cq->sq.desc_buf.size = size;
102 	cq->sq.cmd_buf = devm_kcalloc(ice_hw_to_dev(hw), cq->num_sq_entries,
104 	if (!cq->sq.cmd_buf) {
105 		dmam_free_coherent(ice_hw_to_dev(hw), cq->sq.desc_buf.size,
106 				   cq->sq.desc_buf.va, cq->sq.desc_buf.pa);
107 		cq->sq.desc_buf.va = NULL;
108 		cq->sq.desc_buf.pa = 0;
109 		cq->sq.desc_buf.size = 0;
235 	cq->sq.dma_head = devm_kcalloc(ice_hw_to_dev(hw), cq->num_sq_entries,
236 				       sizeof(cq->sq.desc_buf), GFP_KERNEL);
237 	if (!cq->sq.dma_head)
239 	cq->sq.r.sq_bi = (struct ice_dma_mem *)cq->sq.dma_head;
245 		bi = &cq->sq.r.sq_bi[i];
259 		dmam_free_coherent(ice_hw_to_dev(hw), cq->sq.r.sq_bi[i].size,
260 				   cq->sq.r.sq_bi[i].va, cq->sq.r.sq_bi[i].pa);
261 		cq->sq.r.sq_bi[i].va = NULL;
262 		cq->sq.r.sq_bi[i].pa = 0;
263 		cq->sq.r.sq_bi[i].size = 0;
265 	cq->sq.r.sq_bi = NULL;
266 	devm_kfree(ice_hw_to_dev(hw), cq->sq.dma_head);
267 	cq->sq.dma_head = NULL;
300 	return ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);
365 	if (cq->sq.count > 0) {
377 	cq->sq.next_to_use = 0;
378 	cq->sq.next_to_clean = 0;
396 	cq->sq.count = cq->num_sq_entries;
400 	ICE_FREE_CQ_BUFS(hw, cq, sq);
401 	ice_free_cq_ring(hw, &cq->sq);
480 	if (!cq->sq.count) {
486 	wr32(hw, cq->sq.head, 0);
487 	wr32(hw, cq->sq.tail, 0);
488 	wr32(hw, cq->sq.len, 0);
489 	wr32(hw, cq->sq.bal, 0);
490 	wr32(hw, cq->sq.bah, 0);
492 	cq->sq.count = 0;	/* to indicate uninitialized queue */
495 	ICE_FREE_CQ_BUFS(hw, cq, sq);
496 	ice_free_cq_ring(hw, &cq->sq);
860 	struct ice_ctl_q_ring *sq = &cq->sq;
861 	u16 ntc = sq->next_to_clean;
865 	desc = ICE_CTL_Q_DESC(*sq, ntc);
866 	details = ICE_CTL_Q_DETAILS(*sq, ntc);
868 	while (rd32(hw, cq->sq.head) != ntc) {
869 		ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
873 		if (ntc == sq->count)
875 		desc = ICE_CTL_Q_DESC(*sq, ntc);
876 		details = ICE_CTL_Q_DETAILS(*sq, ntc);
879 	sq->next_to_clean = ntc;
881 	return ICE_CTL_Q_DESC_UNUSED(sq);
942 	return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
978 	if (!cq->sq.count) {
1002 	val = rd32(hw, cq->sq.head);
1010 	details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
1028 	desc_on_ring = ICE_CTL_Q_DESC(cq->sq, cq->sq.next_to_use);
1035 		dma_buf = &cq->sq.r.sq_bi[cq->sq.next_to_use];
1054 	(cq->sq.next_to_use)++;
1055 	if (cq->sq.next_to_use == cq->sq.count)
1056 		cq->sq.next_to_use = 0;
1057 	wr32(hw, cq->sq.tail, cq->sq.next_to_use);
1115 		    rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) {