Lines Matching refs:ICE_M
175 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
1145 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1170 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1214 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1323 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1665 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1667 #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */
2252 #define ICE_AQC_SET_CGU_OUT_CFG_DPLL_SRC_SEL ICE_M(0x1F, 0)
2270 ICE_M(0x1F, ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)
2273 ICE_M(0x7, ICE_AQC_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)
2299 #define ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
2302 ICE_M(0x7, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2305 ICE_M(0x3, ICE_AQC_GET_CGU_DPLL_CONFIG_MODE_SHIFT)
2329 #define ICE_AQC_SET_CGU_DPLL_CONFIG_CLK_REF_SEL ICE_M(0x1F, 0)
2332 ICE_M(0x7, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)
2335 ICE_M(0x3, ICE_AQC_SET_CGU_DPLL_CONFIG_MODE_SHIFT)