intel/i40e/i40e_main.c

360 		if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
362 			    vsi->tx_rings[i]->queue_index) {
363 				tx_ring = vsi->tx_rings[i];
473 	if (!vsi->tx_rings)
481 		ring = READ_ONCE(vsi->tx_rings[i]);
542 			memset(&vsi->tx_rings[i]->stats, 0,
543 			       sizeof(vsi->tx_rings[i]->stats));
544 			memset(&vsi->tx_rings[i]->tx_stats, 0,
545 			       sizeof(vsi->tx_rings[i]->tx_stats));
906 		p = READ_ONCE(vsi->tx_rings[q]);
3338 		err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
3359 	if (vsi->tx_rings) {
3361 			if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
3362 				i40e_free_tx_resources(vsi->tx_rings[i]);
3735 		err = i40e_configure_tx_ring(vsi->tx_rings[i]);
3789 			tx_ring = vsi->tx_rings[i];
3804 			tx_ring = vsi->tx_rings[i];
3913 			ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
4029 	q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
4221 		val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx));
4223 		wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val);
4543 	struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
6067 			tx_ring = vsi->tx_rings[pf_q];
6428 		tx_ring = vsi->tx_rings[pf_q];
7620 		i40e_clean_tx_ring(vsi->tx_rings[i]);
7776 		tx_ring = vsi->tx_rings[pf_q];
7861 				tx_ring = vsi->tx_rings[pf_q];
10724 	if (vsi->tx_rings)
10726 			if (vsi->tx_rings[i])
10728 					  vsi->tx_rings[i]->state);
11437 	vsi->tx_rings = kzalloc(size, GFP_KERNEL);
11438 	if (!vsi->tx_rings)
11440 	next_rings = vsi->tx_rings + vsi->alloc_queue_pairs;
11459 	kfree(vsi->tx_rings);
11569 	kfree(vsi->tx_rings);
11570 	vsi->tx_rings = NULL;
11651 	if (vsi->tx_rings && vsi->tx_rings[0]) {
11653 			kfree_rcu(vsi->tx_rings[i], rcu);
11654 			WRITE_ONCE(vsi->tx_rings[i], NULL);
11691 		WRITE_ONCE(vsi->tx_rings[i], ring++);
13390 	memset(&vsi->tx_rings[queue_pair]->stats, 0,
13391 	       sizeof(vsi->tx_rings[queue_pair]->stats));
13405 	i40e_clean_tx_ring(vsi->tx_rings[queue_pair]);
13582 	err = i40e_configure_tx_ring(vsi->tx_rings[queue_pair]);