intel/i40e/i40e_main.c

354 	u32 head, val;
383 			val = rd32(&pf->hw,
387 			val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
392 			    readl(tx_ring->tail), val);
1009 	u32 val;
1201 	val = rd32(hw, I40E_PRTPM_EEE_STAT);
1203 		       FIELD_GET(I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK, val);
1205 		       FIELD_GET(I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK, val);
3931 			u32 val;
3933 			val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3940 			wr32(hw, I40E_QINT_RQCTL(qp), val);
3944 				val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3951 				wr32(hw, I40E_QINT_TQCTL(nextqp), val);
3954 			val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3963 				val |= (I40E_QUEUE_END_OF_LIST <<
3966 			wr32(hw, I40E_QINT_TQCTL(qp), val);
3981 	u32 val;
3987 	val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK       |
3997 		val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
4000 		val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
4002 	wr32(hw, I40E_PFINT_ICR0_ENA, val);
4075 	u32 val;
4077 	val = I40E_PFINT_DYN_CTL0_INTENA_MASK   |
4081 	wr32(hw, I40E_PFINT_DYN_CTL0, val);
4219 		u32 val;
4221 		val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx));
4222 		val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
4223 		wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val);
4225 		val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx));
4226 		val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
4227 		wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val);
4303 	u32 val, ena_mask;
4367 		val = rd32(hw, I40E_GLGEN_RSTAT);
4368 		val = FIELD_GET(I40E_GLGEN_RSTAT_RESET_TYPE_MASK, val);
4369 		if (val == I40E_RESET_CORER) {
4371 		} else if (val == I40E_RESET_GLOBR) {
4373 		} else if (val == I40E_RESET_EMPR) {
4989 	u32 val, qp;
5025 			val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
5027 				       val);
5028 			val |= I40E_QUEUE_END_OF_LIST
5030 			wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
5035 				val = rd32(hw, I40E_QINT_RQCTL(qp));
5037 				val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK  |
5042 				val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
5045 				wr32(hw, I40E_QINT_RQCTL(qp), val);
5047 				val = rd32(hw, I40E_QINT_TQCTL(qp));
5050 						 val);
5052 				val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK  |
5057 				val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
5060 				wr32(hw, I40E_QINT_TQCTL(qp), val);
5067 		val = rd32(hw, I40E_PFINT_LNKLST0);
5068 		qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK, val);
5069 		val |= I40E_QUEUE_END_OF_LIST
5071 		wr32(hw, I40E_PFINT_LNKLST0, val);
5073 		val = rd32(hw, I40E_QINT_RQCTL(qp));
5074 		val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK  |
5079 		val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
5082 		wr32(hw, I40E_QINT_RQCTL(qp), val);
5084 		val = rd32(hw, I40E_QINT_TQCTL(qp));
5086 		val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK  |
5091 		val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
5094 		wr32(hw, I40E_QINT_TQCTL(qp), val);
9294 	u32 val;
9309 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9310 		val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
9311 		wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
9320 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9321 		val |= I40E_GLGEN_RTRIG_CORER_MASK;
9322 		wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
9611 	u32 val, fcnt_prog;
9613 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
9614 	fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
9624 	u32 val, fcnt_prog;
9626 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
9627 	fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
9628 		    FIELD_GET(I40E_PFQF_FDSTAT_BEST_CNT_MASK, val);
9638 	u32 val, fcnt_prog;
9640 	val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
9641 	fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
9642 		    FIELD_GET(I40E_GLQF_FDCNT_0_BESTCNT_MASK, val);
10156 	u32 val;
10163 	val = rd32(&pf->hw, I40E_PF_ARQLEN);
10164 	oldval = val;
10165 	if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
10168 		val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
10170 	if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
10173 		val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
10176 	if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
10179 		val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
10181 	if (oldval != val)
10182 		wr32(&pf->hw, I40E_PF_ARQLEN, val);
10184 	val = rd32(&pf->hw, I40E_PF_ATQLEN);
10185 	oldval = val;
10186 	if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
10189 		val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
10191 	if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
10194 		val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
10196 	if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
10199 		val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
10201 	if (oldval != val)
10202 		wr32(&pf->hw, I40E_PF_ATQLEN, val);
10268 	val = rd32(hw, I40E_PFINT_ICR0_ENA);
10269 	val |=  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
10270 	wr32(hw, I40E_PFINT_ICR0_ENA, val);
10873 	u32 val;
11087 	val = rd32(hw, I40E_REG_MSS);
11088 	if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11089 		val &= ~I40E_REG_MSS_MIN_MASK;
11090 		val |= I40E_64BYTE_MSS;
11091 		wr32(hw, I40E_REG_MSS, val);
15367 	u32 val = rd32(&pf->hw, I40E_GL_FWSTS);
15369 	if (val & I40E_GL_FWSTS_FWS1B_MASK) {
15605 	u32 val;
15977 	val = rd32(hw, I40E_REG_MSS);
15978 	if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
15979 		val &= ~I40E_REG_MSS_MIN_MASK;
15980 		val |= I40E_64BYTE_MSS;
15981 		wr32(hw, I40E_REG_MSS, val);
16021 		val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
16022 		val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
16023 		wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
16138 	val = FIELD_GET(I40E_PRTGL_SAH_MFS_MASK,
16140 	if (val < MAX_FRAME_SIZE_DEFAULT)
16142 			 pf->hw.port, val, MAX_FRAME_SIZE_DEFAULT);