intel/i40e/i40e_main.c

4056  * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
4069  * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
4302 	u32 icr0, icr0_remaining;
4305 	icr0 = rd32(hw, I40E_PFINT_ICR0);
4309 	if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
4313 	if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
4314 	    (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
4318 	    (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
4325 	if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
4339 	if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4345 	if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
4350 	if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4363 	if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
4379 	if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
4380 		icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
4387 	if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
4396 		icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
4403 	icr0_remaining = icr0 & ena_mask;
4405 		dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",