Lines Matching refs:new_val
1657 u32 new_val;
1668 new_val = new_pb_cfg->shared_pool_low_wm;
1669 if (new_val < old_val) {
1672 reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val);
1681 new_val = new_pb_cfg->shared_pool_low_thresh[i];
1682 if (new_val < old_val) {
1686 new_val);
1691 new_val = new_pb_cfg->tc_pool_low_wm[i];
1692 if (new_val < old_val) {
1696 new_val);
1703 new_val = new_pb_cfg->shared_pool_high_wm;
1704 if (new_val < old_val) {
1707 reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val);
1716 new_val = new_pb_cfg->shared_pool_high_thresh[i];
1717 if (new_val < old_val) {
1721 new_val);
1726 new_val = new_pb_cfg->tc_pool_high_wm[i];
1727 if (new_val < old_val) {
1731 new_val);
1738 new_val = new_pb_cfg->tc_pool_size[i];
1741 reg |= FIELD_PREP(I40E_PRTRPB_DPS_DPS_TCN_MASK, new_val);
1746 new_val = new_pb_cfg->shared_pool_size;
1749 reg |= FIELD_PREP(I40E_PRTRPB_SPS_SPS_MASK, new_val);
1754 new_val = new_pb_cfg->shared_pool_low_wm;
1755 if (new_val > old_val) {
1758 reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val);
1767 new_val = new_pb_cfg->shared_pool_low_thresh[i];
1768 if (new_val > old_val) {
1772 new_val);
1777 new_val = new_pb_cfg->tc_pool_low_wm[i];
1778 if (new_val > old_val) {
1782 new_val);
1789 new_val = new_pb_cfg->shared_pool_high_wm;
1790 if (new_val > old_val) {
1793 reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val);
1802 new_val = new_pb_cfg->shared_pool_high_thresh[i];
1803 if (new_val > old_val) {
1807 new_val);
1812 new_val = new_pb_cfg->tc_pool_high_wm[i];
1813 if (new_val > old_val) {
1817 new_val);