Lines Matching refs:ret_val
180 s32 ret_val = 0;
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
219 if (ret_val)
299 s32 ret_val;
310 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
311 if (ret_val)
314 ret_val = hw->phy.ops.acquire(hw);
315 if (ret_val) {
368 ret_val = -E1000_ERR_PHY;
388 ret_val = -E1000_ERR_PHY;
398 if (!ret_val) {
411 ret_val = e1000e_phy_hw_reset_generic(hw);
412 if (ret_val)
421 ret_val = hw->phy.ops.check_reset_block(hw);
422 if (ret_val)
434 return ret_val;
446 s32 ret_val;
471 ret_val = e1000_init_phy_workarounds_pchlan(hw);
472 if (ret_val)
473 return ret_val;
478 ret_val = e1000e_get_phy_id(hw);
479 if (ret_val)
480 return ret_val;
497 ret_val = e1000_set_mdio_slow_mode_hv(hw);
498 if (ret_val)
499 return ret_val;
500 ret_val = e1000e_get_phy_id(hw);
501 if (ret_val)
502 return ret_val;
525 ret_val = -E1000_ERR_PHY;
529 return ret_val;
541 s32 ret_val;
553 ret_val = e1000e_determine_phy_address(hw);
554 if (ret_val) {
557 ret_val = e1000e_determine_phy_address(hw);
558 if (ret_val) {
560 return ret_val;
568 ret_val = e1000e_get_phy_id(hw);
569 if (ret_val)
570 return ret_val;
786 s32 ret_val;
788 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
789 if (ret_val)
790 return ret_val;
793 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
795 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
797 return ret_val;
843 s32 ret_val;
861 ret_val = hw->phy.ops.acquire(hw);
862 if (ret_val)
863 return ret_val;
865 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
866 if (ret_val)
875 ret_val = e1000_read_emi_reg_locked(hw, lpa,
877 if (ret_val)
881 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
882 if (ret_val)
906 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
908 if (ret_val)
912 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
917 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
918 if (ret_val)
921 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
925 return ret_val;
943 s32 ret_val = 0;
947 ret_val = hw->phy.ops.acquire(hw);
948 if (ret_val)
949 return ret_val;
951 ret_val =
954 if (ret_val)
957 ret_val =
962 if (ret_val)
969 ret_val =
984 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
985 if (ret_val)
986 return ret_val;
1006 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
1007 if (ret_val)
1008 return ret_val;
1014 return ret_val;
1124 s32 ret_val = 0;
1164 ret_val = hw->phy.ops.acquire(hw);
1165 if (ret_val)
1172 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1174 if (ret_val)
1180 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1183 if (ret_val)
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1191 if (ret_val)
1221 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1223 if (ret_val)
1234 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1235 if (ret_val) {
1252 if (ret_val)
1253 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1257 return ret_val;
1277 s32 ret_val = 0;
1308 ret_val = -E1000_ERR_PHY;
1337 ret_val = hw->phy.ops.acquire(hw);
1338 if (ret_val)
1351 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1352 if (ret_val) {
1362 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1364 if (ret_val)
1380 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1381 if (ret_val)
1387 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1388 if (ret_val)
1416 if (ret_val)
1417 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1421 return ret_val;
1435 s32 ret_val, tipg_reg = 0;
1453 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1454 if (ret_val)
1458 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1459 if (ret_val)
1491 ret_val = hw->phy.ops.acquire(hw);
1492 if (ret_val)
1499 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1524 if (ret_val)
1532 ret_val = hw->phy.ops.acquire(hw);
1533 if (ret_val)
1536 ret_val = e1e_rphy_locked(hw,
1539 if (ret_val) {
1548 ret_val =
1554 if (ret_val)
1557 ret_val = hw->phy.ops.acquire(hw);
1558 if (ret_val)
1561 ret_val = e1e_wphy_locked(hw,
1565 if (ret_val)
1591 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1592 if (ret_val)
1599 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1600 if (ret_val)
1628 ret_val = e1000_k1_workaround_lv(hw);
1629 if (ret_val)
1630 return ret_val;
1634 ret_val = e1000_link_stall_workaround_hv(hw);
1635 if (ret_val)
1636 return ret_val;
1663 ret_val = e1000_set_eee_pchlan(hw);
1664 if (ret_val)
1665 return ret_val;
1685 ret_val = e1000e_config_fc_after_link_up(hw);
1686 if (ret_val)
1689 return ret_val;
1693 return ret_val;
1794 s32 ret_val = 0;
1813 ret_val = -E1000_ERR_CONFIG;
1836 ret_val = -E1000_ERR_CONFIG;
1841 if (ret_val)
1844 return ret_val;
1945 s32 ret_val;
1947 ret_val = e1000_acquire_swflag_ich8lan(hw);
1948 if (ret_val)
2056 s32 ret_val;
2058 ret_val = e1000_acquire_swflag_ich8lan(hw);
2060 if (ret_val)
2113 s32 ret_val;
2117 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2118 if (ret_val)
2119 return ret_val;
2152 s32 ret_val = 0;
2164 return ret_val;
2186 return ret_val;
2189 ret_val = hw->phy.ops.acquire(hw);
2190 if (ret_val)
2191 return ret_val;
2222 ret_val = e1000_write_smbus_addr(hw);
2223 if (ret_val)
2227 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2229 if (ret_val)
2239 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2240 if (ret_val)
2243 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2245 if (ret_val)
2257 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2258 if (ret_val)
2264 return ret_val;
2279 s32 ret_val = 0;
2287 ret_val = hw->phy.ops.acquire(hw);
2288 if (ret_val)
2289 return ret_val;
2294 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2296 if (ret_val)
2310 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2311 if (ret_val)
2325 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2326 if (ret_val)
2331 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2332 if (ret_val)
2336 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2341 return ret_val;
2356 s32 ret_val;
2362 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2364 if (ret_val)
2365 return ret_val;
2372 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2374 if (ret_val)
2375 return ret_val;
2407 s32 ret_val = 0;
2412 return ret_val;
2414 ret_val = hw->phy.ops.acquire(hw);
2415 if (ret_val)
2416 return ret_val;
2430 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2431 if (ret_val)
2457 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2462 return ret_val;
2471 s32 ret_val;
2474 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2475 if (ret_val)
2476 return ret_val;
2480 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2482 return ret_val;
2493 s32 ret_val = 0;
2501 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2502 if (ret_val)
2503 return ret_val;
2510 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2511 if (ret_val)
2512 return ret_val;
2515 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2516 if (ret_val)
2517 return ret_val;
2526 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2527 if (ret_val)
2528 return ret_val;
2533 ret_val = hw->phy.ops.acquire(hw);
2534 if (ret_val)
2535 return ret_val;
2538 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2540 if (ret_val)
2541 return ret_val;
2546 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2547 if (ret_val)
2548 return ret_val;
2551 ret_val = hw->phy.ops.acquire(hw);
2552 if (ret_val)
2553 return ret_val;
2554 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2555 if (ret_val)
2557 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2558 if (ret_val)
2562 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2566 return ret_val;
2577 s32 ret_val;
2579 ret_val = hw->phy.ops.acquire(hw);
2580 if (ret_val)
2582 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2583 if (ret_val)
2615 s32 ret_val = 0;
2625 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2626 if (ret_val)
2627 return ret_val;
2664 ret_val = e1000e_read_kmrn_reg(hw,
2667 if (ret_val)
2668 return ret_val;
2669 ret_val = e1000e_write_kmrn_reg(hw,
2672 if (ret_val)
2673 return ret_val;
2674 ret_val = e1000e_read_kmrn_reg(hw,
2677 if (ret_val)
2678 return ret_val;
2681 ret_val = e1000e_write_kmrn_reg(hw,
2684 if (ret_val)
2685 return ret_val;
2691 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2692 if (ret_val)
2693 return ret_val;
2696 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2697 if (ret_val)
2698 return ret_val;
2702 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2703 if (ret_val)
2704 return ret_val;
2705 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2706 if (ret_val)
2707 return ret_val;
2709 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2710 if (ret_val)
2711 return ret_val;
2722 ret_val = e1000e_read_kmrn_reg(hw,
2725 if (ret_val)
2726 return ret_val;
2727 ret_val = e1000e_write_kmrn_reg(hw,
2730 if (ret_val)
2731 return ret_val;
2732 ret_val = e1000e_read_kmrn_reg(hw,
2735 if (ret_val)
2736 return ret_val;
2739 ret_val = e1000e_write_kmrn_reg(hw,
2742 if (ret_val)
2743 return ret_val;
2748 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2749 if (ret_val)
2750 return ret_val;
2753 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2754 if (ret_val)
2755 return ret_val;
2759 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2760 if (ret_val)
2761 return ret_val;
2762 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2763 if (ret_val)
2764 return ret_val;
2766 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2767 if (ret_val)
2768 return ret_val;
2783 s32 ret_val = 0;
2789 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2790 if (ret_val)
2791 return ret_val;
2793 ret_val = hw->phy.ops.acquire(hw);
2794 if (ret_val)
2795 return ret_val;
2797 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2798 if (ret_val)
2801 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2805 return ret_val;
2817 s32 ret_val = 0;
2824 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2825 if (ret_val)
2826 return ret_val;
2835 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2836 if (ret_val)
2837 return ret_val;
2839 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2840 if (ret_val)
2841 return ret_val;
2852 return ret_val;
2917 s32 ret_val = 0;
2929 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2930 if (ret_val)
2931 return ret_val;
2934 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2935 if (ret_val)
2936 return ret_val;
2950 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2951 if (ret_val)
2952 return ret_val;
2955 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2965 ret_val = hw->phy.ops.acquire(hw);
2966 if (ret_val)
2967 return ret_val;
2968 ret_val = e1000_write_emi_reg_locked(hw,
2974 return ret_val;
2987 s32 ret_val = 0;
2994 ret_val = e1000e_phy_hw_reset_generic(hw);
2995 if (ret_val)
2996 return ret_val;
3014 s32 ret_val;
3017 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
3018 if (ret_val)
3019 return ret_val;
3049 s32 ret_val = 0;
3071 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3072 if (ret_val)
3073 return ret_val;
3075 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3076 if (ret_val)
3077 return ret_val;
3091 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3093 if (ret_val)
3094 return ret_val;
3097 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3099 if (ret_val)
3100 return ret_val;
3102 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3104 if (ret_val)
3105 return ret_val;
3108 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3110 if (ret_val)
3111 return ret_val;
3135 s32 ret_val = 0;
3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3155 if (ret_val)
3156 return ret_val;
3159 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3161 if (ret_val)
3162 return ret_val;
3164 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3166 if (ret_val)
3167 return ret_val;
3170 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3172 if (ret_val)
3173 return ret_val;
3191 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3192 if (ret_val)
3193 return ret_val;
3196 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3199 return ret_val;
3218 s32 ret_val;
3236 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3238 if (ret_val)
3239 return ret_val;
3248 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3251 if (ret_val)
3252 return ret_val;
3281 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3283 if (ret_val)
3284 return ret_val;
3292 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3295 if (ret_val)
3296 return ret_val;
3323 s32 ret_val = 0;
3332 ret_val = -E1000_ERR_NVM;
3338 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3339 if (ret_val) {
3347 ret_val = 0;
3357 ret_val =
3361 if (ret_val)
3372 ret_val =
3376 if (ret_val)
3395 if (ret_val)
3396 e_dbg("NVM read error: %d\n", ret_val);
3398 return ret_val;
3416 s32 ret_val = 0;
3423 ret_val = -E1000_ERR_NVM;
3429 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3430 if (ret_val) {
3438 ret_val = 0;
3443 ret_val = e1000_read_flash_word_ich8lan(hw,
3446 if (ret_val)
3455 if (ret_val)
3456 e_dbg("NVM read error: %d\n", ret_val);
3458 return ret_val;
3471 s32 ret_val = -E1000_ERR_NVM;
3507 ret_val = 0;
3517 ret_val = 0;
3522 if (!ret_val) {
3537 return ret_val;
3625 s32 ret_val;
3634 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3636 if (ret_val)
3637 return ret_val;
3660 s32 ret_val = -E1000_ERR_NVM;
3672 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3673 if (ret_val)
3684 ret_val =
3693 if (!ret_val) {
3717 return ret_val;
3735 s32 ret_val = -E1000_ERR_NVM;
3746 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3747 if (ret_val)
3763 ret_val =
3772 if (!ret_val) {
3792 return ret_val;
3845 s32 ret_val;
3848 ret_val = e1000e_update_nvm_checksum_generic(hw);
3849 if (ret_val)
3861 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3862 if (ret_val) {
3870 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3871 if (ret_val)
3876 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3877 if (ret_val)
3885 ret_val = e1000_read_flash_dword_ich8lan(hw,
3898 if (ret_val)
3918 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3920 if (ret_val)
3927 if (ret_val) {
3942 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3944 if (ret_val)
3948 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3950 if (ret_val)
3955 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3957 if (ret_val)
3961 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3963 if (ret_val)
3978 if (!ret_val) {
3984 if (ret_val)
3985 e_dbg("NVM update error: %d\n", ret_val);
3987 return ret_val;
4006 s32 ret_val;
4009 ret_val = e1000e_update_nvm_checksum_generic(hw);
4010 if (ret_val)
4022 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4023 if (ret_val) {
4031 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4032 if (ret_val)
4037 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4038 if (ret_val)
4045 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4048 if (ret_val)
4067 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4070 if (ret_val)
4074 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4077 if (ret_val)
4084 if (ret_val) {
4096 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4097 if (ret_val)
4101 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4104 if (ret_val)
4113 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4114 if (ret_val)
4129 if (!ret_val) {
4135 if (ret_val)
4136 e_dbg("NVM update error: %d\n", ret_val);
4138 return ret_val;
4151 s32 ret_val;
4180 ret_val = e1000_read_nvm(hw, word, 1, &data);
4181 if (ret_val)
4182 return ret_val;
4189 ret_val = e1000_write_nvm(hw, word, 1, &data);
4190 if (ret_val)
4191 return ret_val;
4192 ret_val = e1000e_update_nvm_checksum(hw);
4193 if (ret_val)
4194 return ret_val;
4257 s32 ret_val;
4274 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4275 if (ret_val)
4309 ret_val =
4312 if (!ret_val)
4330 return ret_val;
4347 s32 ret_val;
4359 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4360 if (ret_val)
4391 ret_val =
4395 if (!ret_val)
4414 return ret_val;
4445 s32 ret_val;
4450 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4452 if (!ret_val)
4453 return ret_val;
4457 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4458 if (!ret_val)
4479 s32 ret_val;
4482 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4483 if (!ret_val)
4484 return ret_val;
4489 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4490 if (!ret_val)
4515 s32 ret_val;
4564 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4565 if (ret_val)
4566 return ret_val;
4591 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4592 if (!ret_val)
4604 return ret_val;
4622 s32 ret_val;
4624 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4625 if (ret_val) {
4627 return ret_val;
4652 s32 ret_val;
4658 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4659 if (ret_val)
4660 return ret_val;
4718 s32 ret_val;
4720 ret_val = e1000e_get_bus_info_pcie(hw);
4730 return ret_val;
4745 s32 ret_val;
4750 ret_val = e1000e_disable_pcie_master(hw);
4751 if (ret_val)
4777 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4778 if (ret_val)
4779 return ret_val;
4803 ret_val = e1000_acquire_swflag_ich8lan(hw);
4817 if (!ret_val)
4821 ret_val = hw->phy.ops.get_cfg_done(hw);
4822 if (ret_val)
4823 return ret_val;
4825 ret_val = e1000_post_phy_reset_ich8lan(hw);
4826 if (ret_val)
4827 return ret_val;
4863 s32 ret_val;
4869 ret_val = mac->ops.id_led_init(hw);
4871 if (ret_val)
4890 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4891 if (ret_val)
4892 return ret_val;
4896 ret_val = mac->ops.setup_link(hw);
4941 return ret_val;
5033 s32 ret_val;
5058 ret_val = hw->mac.ops.setup_physical_interface(hw);
5059 if (ret_val)
5060 return ret_val;
5069 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5071 if (ret_val)
5072 return ret_val;
5089 s32 ret_val;
5101 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5102 if (ret_val)
5103 return ret_val;
5104 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5106 if (ret_val)
5107 return ret_val;
5109 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5111 if (ret_val)
5112 return ret_val;
5116 ret_val = e1000e_copper_link_setup_igp(hw);
5117 if (ret_val)
5118 return ret_val;
5122 ret_val = e1000e_copper_link_setup_m88(hw);
5123 if (ret_val)
5124 return ret_val;
5128 ret_val = e1000_copper_link_setup_82577(hw);
5129 if (ret_val)
5130 return ret_val;
5133 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5134 if (ret_val)
5135 return ret_val;
5151 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5152 if (ret_val)
5153 return ret_val;
5173 s32 ret_val;
5180 ret_val = e1000_copper_link_setup_82577(hw);
5181 if (ret_val)
5182 return ret_val;
5200 s32 ret_val;
5202 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5203 if (ret_val)
5204 return ret_val;
5208 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5211 return ret_val;
5233 s32 ret_val;
5244 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5250 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5251 if (ret_val)
5252 return ret_val;
5254 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5255 if (ret_val)
5256 return ret_val;
5365 s32 ret_val;
5371 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5373 if (ret_val)
5376 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5378 if (ret_val)
5402 s32 ret_val;
5420 ret_val = hw->phy.ops.acquire(hw);
5421 if (ret_val)
5427 ret_val =
5431 if (ret_val)
5504 ret_val = hw->phy.ops.acquire(hw);
5505 if (ret_val)
5524 s32 ret_val;
5529 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5530 if (ret_val) {
5531 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5543 ret_val = hw->phy.ops.acquire(hw);
5544 if (ret_val) {
5558 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5559 if (ret_val)
5568 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5569 if (ret_val)
5574 if (ret_val)
5575 e_dbg("Error %d in resume workarounds\n", ret_val);
5724 s32 ret_val = 0;
5734 ret_val = e1000e_get_auto_rd_done(hw);
5735 if (ret_val) {
5741 ret_val = 0;
5762 ret_val = -E1000_ERR_CONFIG;
5766 return ret_val;
5794 s32 ret_val;
5817 ret_val = hw->phy.ops.acquire(hw);
5818 if (ret_val)
5820 ret_val = hw->phy.ops.set_page(hw,
5822 if (ret_val)