hisilicon/hns/hns_dsaf_ppe.c

58 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
60 	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
71 	struct ppe_common_cb *ppe_common;
79 	ppe_common = devm_kzalloc(dsaf_dev->dev,
80 				  struct_size(ppe_common, ppe_cb, ppe_num),
82 	if (!ppe_common)
85 	ppe_common->ppe_num = ppe_num;
86 	ppe_common->dsaf_dev = dsaf_dev;
87 	ppe_common->comm_index = comm_index;
89 		ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
91 		ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
92 	ppe_common->dev = dsaf_dev->dev;
94 	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
96 	dsaf_dev->ppe_common[comm_index] = ppe_common;
104 	dsaf_dev->ppe_common[comm_index] = NULL;
107 static u8 __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
110 	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
113 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
117 	u32 ppe_num = ppe_common->ppe_num;
120 		ppe_cb = &ppe_common->ppe_cb[i];
121 		ppe_cb->dev = ppe_common->dev;
123 		ppe_cb->ppe_common_cb = ppe_common;
125 		ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
152 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
155 	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
162  * @ppe_common: ppe common device
165 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
167 	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
173 		dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
190  * @ppe_common: ppe common device
194 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
197 	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
205 	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
210 			hns_ppe_set_qid(ppe_common, 0);
239 			dev_err(ppe_common->dev,
244 		hns_ppe_set_qid_mode(ppe_common, qid_mode);
247 	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
358 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
362 	for (i = 0; i < ppe_common->ppe_num; i++) {
363 		if (ppe_common->dsaf_dev->mac_cb[i])
364 			hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
365 		memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
374 		if (dsaf_dev->ppe_common[i])
375 			hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
391 	struct ppe_common_cb *ppe_common;
393 	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
394 	ret = hns_ppe_common_init_hw(ppe_common);
398 	for (i = 0; i < ppe_common->ppe_num; i++) {
401 			hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
519 		hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
542 	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
548 	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
549 	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
550 	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
551 	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
552 	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
556 		regs[5 + i] = dsaf_read_dev(ppe_common, offset);
559 				= dsaf_read_dev(ppe_common, offset);
562 				= dsaf_read_dev(ppe_common, offset);
565 				= dsaf_read_dev(ppe_common, offset);