ethernet/hisilicon/hisi_femac.c

110 	void __iomem *glb_base;
130 	val = readl(priv->glb_base + GLB_IRQ_ENA);
131 	writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
138 	val = readl(priv->glb_base + GLB_IRQ_ENA);
139 	writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
254 	while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {
260 		writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
315 		ints = readl(priv->glb_base + GLB_IRQ_RAW);
317 		       priv->glb_base + GLB_IRQ_RAW);
335 	ints = readl(priv->glb_base + GLB_IRQ_RAW);
339 		       priv->glb_base + GLB_IRQ_RAW);
435 	writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
438 	writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
447 	val = readl(priv->glb_base + GLB_SOFT_RESET);
449 	writel(val, priv->glb_base + GLB_SOFT_RESET);
454 	writel(val, priv->glb_base + GLB_SOFT_RESET);
476 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
571 	val = readl(priv->glb_base + GLB_MAC_H16(reg_n));
576 	writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
590 	writel(val, priv->glb_base + low);
592 	val = readl(priv->glb_base + high);
596 	writel(val, priv->glb_base + high);
604 	val = readl(priv->glb_base + GLB_FWCTRL);
609 	writel(val, priv->glb_base + GLB_FWCTRL);
618 	val = readl(priv->glb_base + GLB_MACTCTRL);
636 	writel(val, priv->glb_base + GLB_MACTCTRL);
645 	val = readl(priv->glb_base + GLB_MACTCTRL);
662 	writel(val, priv->glb_base + GLB_MACTCTRL);
743 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
746 	val = readl(priv->glb_base + GLB_FWCTRL);
749 	writel(val, priv->glb_base + GLB_FWCTRL);
751 	val = readl(priv->glb_base + GLB_MACTCTRL);
753 	writel(val, priv->glb_base + GLB_MACTCTRL);
794 	priv->glb_base = devm_platform_ioremap_resource(pdev, 1);
795 	if (IS_ERR(priv->glb_base)) {
796 		ret = PTR_ERR(priv->glb_base);