dec/tulip/tulip_core.c

285 	void __iomem *ioaddr = tp->base_addr;
304 		iowrite32(0x00040000, ioaddr + CSR6);
307 	iowrite32(0x00000001, ioaddr + CSR0);
314 	iowrite32(tp->csr0, ioaddr + CSR0);
321 	iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
322 	iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
330 			iowrite32(0, ioaddr + CSR13);
331 			iowrite32(addr_low,  ioaddr + CSR14);
332 			iowrite32(1, ioaddr + CSR13);
333 			iowrite32(addr_high, ioaddr + CSR14);
335 			iowrite32(addr_low,  ioaddr + 0xA4);
336 			iowrite32(addr_high, ioaddr + 0xA8);
337 			iowrite32(0, ioaddr + CSR27);
338 			iowrite32(0, ioaddr + CSR28);
410 			iowrite32(0x0000, ioaddr + CSR13);
411 			iowrite32(0x0000, ioaddr + CSR14);
412 			iowrite32(0x0008, ioaddr + CSR15);
423 			iowrite32(csr6_mask_defstate, ioaddr + CSR6);
426 			iowrite32(0x0000, ioaddr + CSR13);
427 			iowrite32(0x0000, ioaddr + CSR14);
434 	        iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
435 	        iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
441 			iowrite32(0x0001, ioaddr + CSR15);
442 		} else if (ioread32(ioaddr + CSR5) & TPLnkPass)
446 			iowrite32(0x32, ioaddr + CSR12);
448 			iowrite32(0x0001B078, ioaddr + 0xB8);
449 			iowrite32(0x0201B078, ioaddr + 0xB8);
456 		iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
461 		iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
462 		iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
465 		iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
477 	iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
480 	iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
481 	iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
483 	iowrite32(0, ioaddr + CSR2);		/* Rx poll demand */
487 			   ioread32(ioaddr + CSR0),
488 			   ioread32(ioaddr + CSR5),
489 			   ioread32(ioaddr + CSR6));
529 	void __iomem *ioaddr = tp->base_addr;
544 			 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
545 			 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
546 			 ioread32(ioaddr + CSR15));
553 			 (int)ioread32(ioaddr + CSR5),
554 			 (int)ioread32(ioaddr + CSR6),
555 			 (int)ioread32(ioaddr + CSR7),
556 			 (int)ioread32(ioaddr + CSR12));
560 			 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
593 	tulip_tx_timeout_complete(tp, ioaddr);
741 	void __iomem *ioaddr = tp->base_addr;
757 	iowrite32 (0x00000000, ioaddr + CSR7);
768 	if (ioread32(ioaddr + CSR6) != 0xffffffff)
769 		dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
822 	void __iomem *ioaddr = tp->base_addr;
830 			   ioread32 (ioaddr + CSR5));
842 	void __iomem *ioaddr = tp->base_addr;
849 		dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
900 	void __iomem *ioaddr = tp->base_addr;
920 			int csr12 = ioread32 (ioaddr + CSR12);
921 			int csr14 = ioread32 (ioaddr + CSR14);
941 					((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
1057 	void __iomem *ioaddr = tp->base_addr;
1060 	csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1102 				iowrite32(2, ioaddr + CSR13);
1103 				iowrite32(mc_filter[0], ioaddr + CSR14);
1104 				iowrite32(3, ioaddr + CSR13);
1105 				iowrite32(mc_filter[1], ioaddr + CSR14);
1107 				iowrite32(mc_filter[0], ioaddr + CSR27);
1108 				iowrite32(mc_filter[1], ioaddr + CSR28);
1171 			iowrite32(0, ioaddr + CSR1);
1177 	iowrite32(csr6, ioaddr + CSR6);
1303 	void __iomem *ioaddr;
1419 	ioaddr = pcim_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1421 	if (!ioaddr)
1457 	tp->base_addr = ioaddr;
1494 	ioread32(ioaddr + CSR8);
1506 			iowrite32(0x600 | i, ioaddr + 0x98);
1508 				value = ioread32(ioaddr + CSR9);
1516 		put_unaligned_le32(ioread32(ioaddr + 0xA4), addr);
1517 		put_unaligned_le16(ioread32(ioaddr + 0xA8), addr + 4);
1726 			iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1730 			iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1731 			iowrite32(0x0000, ioaddr + CSR13);
1732 			iowrite32(0x0000, ioaddr + CSR14);
1733 			iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1739 		iowrite32(0x0000, ioaddr + CSR13);
1740 		iowrite32(0x0000, ioaddr + CSR14);
1746 			iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1747 			iowrite32(0x30, ioaddr + CSR12);
1748 			iowrite32(0x0001F078, ioaddr + CSR6);
1749 			iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1754 		iowrite32(0x00000000, ioaddr + CSR6);
1755 		iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1756 		iowrite32(0x00000001, ioaddr + CSR13);
1760 		iowrite32(0x01a80000, ioaddr + CSR6);
1761 		iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1762 		iowrite32(0x00001000, ioaddr + CSR12);
1781 	void __iomem *ioaddr = tp->base_addr;
1786 		tmp = ioread32(ioaddr + CSR18);
1789 		iowrite32(tmp, ioaddr + CSR18);
1792 		tmp = ioread32(ioaddr + CSR13);
1800 		iowrite32(tmp, ioaddr + CSR13);
1833 	void __iomem *ioaddr = tp->base_addr;
1854 		tmp = ioread32(ioaddr + CSR20);
1856 		iowrite32(tmp, ioaddr + CSR20);