cisco/enic/enic_main.c

329 		dma_unmap_single(&enic->pdev->dev, buf->dma_addr, buf->len,
332 		dma_unmap_page(&enic->pdev->dev, buf->dma_addr, buf->len,
549 	dma_addr_t dma_addr;
554 		dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 0,
557 		if (unlikely(enic_dma_map_check(enic, dma_addr)))
559 		enic_queue_wq_desc_cont(wq, skb, dma_addr, skb_frag_size(frag),
574 	dma_addr_t dma_addr;
577 	dma_addr = dma_map_single(&enic->pdev->dev, skb->data, head_len,
579 	if (unlikely(enic_dma_map_check(enic, dma_addr)))
587 	enic_queue_wq_desc(wq, skb, dma_addr, head_len,	vlan_tag_insert,
605 	dma_addr_t dma_addr;
608 	dma_addr = dma_map_single(&enic->pdev->dev, skb->data, head_len,
610 	if (unlikely(enic_dma_map_check(enic, dma_addr)))
618 	enic_queue_wq_desc_csum_l4(wq, skb, dma_addr, head_len,	csum_offset,
678 	dma_addr_t dma_addr;
695 		dma_addr = dma_map_single(&enic->pdev->dev,
698 		if (unlikely(enic_dma_map_check(enic, dma_addr)))
700 		enic_queue_wq_desc_tso(wq, skb, dma_addr, len, mss, hdr_len,
721 			dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag,
724 			if (unlikely(enic_dma_map_check(enic, dma_addr)))
726 			enic_queue_wq_desc_cont(wq, skb, dma_addr, len,
752 	dma_addr_t dma_addr;
755 	dma_addr = dma_map_single(&enic->pdev->dev, skb->data, head_len,
757 	if (unlikely(enic_dma_map_check(enic, dma_addr)))
760 	enic_queue_wq_desc_ex(wq, skb, dma_addr, head_len, mss_or_csum, 0,
1229 	dma_unmap_single(&enic->pdev->dev, buf->dma_addr, buf->len,
1242 	dma_addr_t dma_addr;
1246 		enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr,
1255 	dma_addr = dma_map_single(&enic->pdev->dev, skb->data, len,
1257 	if (unlikely(enic_dma_map_check(enic, dma_addr))) {
1263 		dma_addr, len);
1288 	dma_sync_single_for_cpu(&enic->pdev->dev, buf->dma_addr, len,
1338 		dma_unmap_single(&enic->pdev->dev, buf->dma_addr, buf->len,
1353 			dma_unmap_single(&enic->pdev->dev, buf->dma_addr,
1427 		dma_unmap_single(&enic->pdev->dev, buf->dma_addr, buf->len,