Lines Matching refs:padap
478 struct adapter *padap = pdbg_init->adap;
480 if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
515 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
520 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
524 rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
537 int cudbg_fill_meminfo(struct adapter *padap,
558 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
560 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
571 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A);
581 if (is_t5(padap->params.chip)) {
583 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
594 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
605 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
616 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
633 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
634 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
635 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
636 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
637 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
638 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
639 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
640 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
641 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
644 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
646 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
647 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
650 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
652 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
653 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
656 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
657 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
658 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
659 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
661 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
662 md->base = t4_read_reg(padap,
673 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
674 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
688 if (!is_t4(padap->params.chip)) {
689 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
690 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
693 if (is_t5(padap->params.chip)) {
701 md->base = BASEADDR_G(t4_read_reg(padap,
709 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
712 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
716 md->base = padap->vres.ocq.start;
717 if (padap->vres.ocq.size)
718 md->limit = md->base + padap->vres.ocq.size - 1;
738 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
739 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
743 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
744 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
748 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
751 FREERXPAGECOUNT_G(t4_read_reg(padap,
756 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
759 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
760 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
763 FREETXPAGECOUNT_G(t4_read_reg(padap,
773 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
775 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A));
778 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
779 lo = t4_read_reg(padap,
782 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
783 if (is_t5(padap->params.chip)) {
794 for (i = 0; i < padap->params.arch.nchan; i++) {
795 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
796 lo = t4_read_reg(padap,
799 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
800 if (is_t5(padap->params.chip)) {
818 struct adapter *padap = pdbg_init->adap;
823 if (is_t4(padap->params.chip))
825 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
831 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
839 struct adapter *padap = pdbg_init->adap;
844 rc = t4_init_devlog_params(padap);
850 dparams = &padap->params.devlog;
857 spin_lock(&padap->win0_lock);
858 rc = t4_memory_rw(padap, padap->params.drv_memwin,
863 spin_unlock(&padap->win0_lock);
877 struct adapter *padap = pdbg_init->adap;
882 if (is_t6(padap->params.chip)) {
883 size = padap->params.cim_la_size / 10 + 1;
886 size = padap->params.cim_la_size / 8;
895 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
903 rc = t4_cim_read_la(padap,
918 struct adapter *padap = pdbg_init->adap;
927 t4_cim_read_ma_la(padap,
938 struct adapter *padap = pdbg_init->adap;
949 cim_qcfg_data->chip = padap->params.chip;
950 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
958 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
967 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
976 struct adapter *padap = pdbg_init->adap;
988 no_of_read_words = t4_read_cim_ibq(padap, qid,
1045 u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
1049 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
1051 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
1060 struct adapter *padap = pdbg_init->adap;
1066 qsize = cudbg_cim_obq_size(padap, qid);
1072 no_of_read_words = t4_read_cim_obq(padap, qid,
1143 static int cudbg_meminfo_get_mem_index(struct adapter *padap,
1158 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
1181 static int cudbg_get_mem_region(struct adapter *padap,
1190 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
1232 static int cudbg_get_mem_relative(struct adapter *padap,
1239 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
1257 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
1265 rc = cudbg_fill_meminfo(padap, &meminfo);
1269 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
1280 return cudbg_get_mem_relative(padap, &meminfo, mem_type,
1374 struct adapter *padap = pdbg_init->adap;
1384 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
1422 spin_lock(&padap->win0_lock);
1425 spin_unlock(&padap->win0_lock);
1448 struct adapter *padap = pdbg_init->adap;
1453 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1463 struct adapter *padap = pdbg_init->adap;
1469 rc = cudbg_fill_meminfo(padap, &mem_info);
1476 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1549 struct adapter *padap = pdbg_init->adap;
1553 nentries = t4_chip_rss_size(padap);
1559 rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1572 struct adapter *padap = pdbg_init->adap;
1577 vf_count = padap->params.arch.vfcount;
1586 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1595 struct adapter *padap = pdbg_init->adap;
1604 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1612 struct adapter *padap = pdbg_init->adap;
1623 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1624 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1632 struct adapter *padap = pdbg_init->adap;
1637 if (!padap->params.vpd.cclk)
1647 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1648 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1649 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1651 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1660 struct adapter *padap = pdbg_init->adap;
1666 if (is_t5(padap->params.chip))
1684 if (is_t5(padap->params.chip))
1686 else if (is_t6(padap->params.chip))
1693 if (is_t5(padap->params.chip)) {
1698 } else if (is_t6(padap->params.chip)) {
1704 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1710 if (is_t5(padap->params.chip))
1712 else if (is_t6(padap->params.chip))
1719 if (is_t5(padap->params.chip)) {
1724 } else if (is_t6(padap->params.chip)) {
1730 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1736 if (is_t5(padap->params.chip))
1739 else if (is_t6(padap->params.chip))
1747 if (is_t5(padap->params.chip)) {
1754 } else if (is_t6(padap->params.chip)) {
1762 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1769 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
1785 t4_write_reg(padap, qbase->reg_addr, func);
1787 *buff = t4_read_reg(padap, qbase->reg_data[i]);
1794 struct adapter *padap = pdbg_init->adap;
1806 for_each_port(padap, i) {
1807 padap_running = netif_running(padap->port[i]);
1829 t4_read_indirect(padap,
1838 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5 &&
1850 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1853 for (i = 0; i < padap->params.arch.vfcount; i++)
1854 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1857 sge_qbase->vfcount = padap->params.arch.vfcount;
1867 struct adapter *padap = pdbg_init->adap;
1878 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1887 struct adapter *padap = pdbg_init->adap;
1898 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1899 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1907 struct adapter *padap = pdbg_init->adap;
1927 rc = cudbg_fill_meminfo(padap, meminfo_buff);
1942 struct adapter *padap = pdbg_init->adap;
1954 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1964 struct adapter *padap = pdbg_init->adap;
1970 if (!padap->params.vpd.cclk)
1979 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
1980 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1987 t4_read_reg(padap, TP_DACK_TIMER_A);
1989 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1991 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1993 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1995 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1997 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1999 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
2001 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
2003 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
2012 struct adapter *padap = pdbg_init->adap;
2034 t4_read_indirect(padap,
2053 t4_read_indirect(padap,
2068 struct adapter *padap = pdbg_init->adap;
2090 t4_read_indirect(padap,
2109 t4_read_indirect(padap,
2124 struct adapter *padap = pdbg_init->adap;
2158 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
2167 if (is_t5(padap->params.chip)) {
2168 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
2169 } else if (is_t6(padap->params.chip)) {
2171 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
2172 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
2176 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
2190 tid->ntids = padap->tids.ntids;
2191 tid->nstids = padap->tids.nstids;
2192 tid->stid_base = padap->tids.stid_base;
2193 tid->hash_base = padap->tids.hash_base;
2195 tid->natids = padap->tids.natids;
2196 tid->nftids = padap->tids.nftids;
2197 tid->ftid_base = padap->tids.ftid_base;
2198 tid->aftid_base = padap->tids.aftid_base;
2199 tid->aftid_end = padap->tids.aftid_end;
2201 tid->sftid_base = padap->tids.sftid_base;
2202 tid->nsftids = padap->tids.nsftids;
2204 tid->flags = padap->flags;
2205 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
2206 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
2207 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
2216 struct adapter *padap = pdbg_init->adap;
2231 t4_hw_pci_read_cfg4(padap, j, value);
2258 static int cudbg_get_ctxt_region_info(struct adapter *padap,
2268 rc = cudbg_fill_meminfo(padap, &meminfo);
2277 rc = cudbg_get_mem_region(padap, &meminfo, j,
2282 rc = cudbg_get_mem_relative(padap, &meminfo, j,
2301 value = t4_read_reg(padap, SGE_FLM_CFG_A);
2317 int cudbg_dump_context_size(struct adapter *padap)
2325 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
2346 struct adapter *padap = pdbg_init->adap;
2357 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
2359 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
2395 struct adapter *padap = pdbg_init->adap;
2405 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
2409 rc = cudbg_dump_context_size(padap);
2453 t4_sge_ctxt_flush(padap, padap->mbox, i);
2455 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
2511 static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2514 if (is_t5(padap->params.chip)) {
2515 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2517 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2519 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2521 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2524 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2526 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2528 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2530 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2533 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2534 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2535 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2536 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2542 struct adapter *padap = pdbg_init->adap;
2547 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2561 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2562 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2564 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2565 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2586 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2587 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2589 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2590 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2597 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2598 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2605 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2606 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2608 if (is_t5(padap->params.chip))
2610 else if (is_t6(padap->params.chip))
2631 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2635 cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2648 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2657 tcam->rplc_size = padap->params.arch.mps_rplc_size;
2665 struct adapter *padap = pdbg_init->adap;
2671 n = padap->params.arch.mps_tcam_size;
2702 struct adapter *padap = pdbg_init->adap;
2710 rc = t4_get_raw_vpd_params(padap, &vpd);
2714 rc = t4_get_fw_version(padap, &fw_vers);
2718 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2738 vpd_data->scfg_vers = t4_read_reg(padap, PCIE_STATIC_SPARE2_A);
2750 struct adapter *padap = pdbg_init->adap;
2756 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2760 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2764 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2770 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2778 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2785 tid_data->data[i] = t4_read_reg(padap,
2836 void cudbg_fill_le_tcam_info(struct adapter *padap,
2842 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
2846 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2850 if (is_t6(padap->params.chip))
2851 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A);
2853 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2857 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2861 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2865 value = t4_read_reg(padap, LE_DB_CONFIG_A);
2867 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2868 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2878 if (is_t6(padap->params.chip))
2886 if (is_t6(padap->params.chip))
2894 struct adapter *padap = pdbg_init->adap;
2902 cudbg_fill_le_tcam_info(padap, &tcam_region);
2927 if (is_t6(padap->params.chip) &&
2949 struct adapter *padap = pdbg_init->adap;
2959 t4_read_cong_tbl(padap, (void *)temp_buff.data);
2967 struct adapter *padap = pdbg_init->adap;
2973 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2991 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
3006 t4_read_indirect(padap, ma_fli->ireg_addr,
3021 struct adapter *padap = pdbg_init->adap;
3043 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
3046 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
3049 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
3054 t4_read_reg(padap,
3059 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
3061 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A);
3063 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A);
3065 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A);
3067 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A);
3069 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A);
3071 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A);
3073 t4_read_reg(padap, PM_RX_BASE_ADDR);
3083 struct adapter *padap = pdbg_init->adap;
3091 if (is_t5(padap->params.chip))
3094 else if (is_t6(padap->params.chip))
3110 if (is_t5(padap->params.chip)) {
3118 } else if (is_t6(padap->params.chip)) {
3147 rc = t4_cim_read(padap,
3164 struct adapter *padap = pdbg_init->adap;
3180 rc = t4_cim_read(padap, addr + (i * 4), 1,
3193 rc = t4_cim_read(padap, addr + (i * 4), 1,
3205 rc = t4_cim_read(padap, addr + (i * 4), 1,
3217 rc = t4_cim_read(padap, addr + (i * 4), 1,
3232 struct adapter *padap = pdbg_init->adap;
3243 log = padap->mbox_log;
3244 mbox_cmds = padap->mbox_log->size;
3276 struct adapter *padap = pdbg_init->adap;
3282 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
3300 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
3308 void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
3367 struct adapter *padap = pdbg_init->adap;
3372 struct sge *s = &padap->sge;
3377 cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
3435 for (i = 0; i < padap->params.nports; i++)
3509 if (!padap->tc_mqprio)
3512 mutex_lock(&padap->tc_mqprio->mqprio_mutex);
3531 mutex_unlock(&padap->tc_mqprio->mqprio_mutex);
3578 struct adapter *padap = pdbg_init->adap;
3579 u32 count = padap->params.sf_size, n;
3594 rc = t4_read_flash(padap, addr, n, (u32 *)temp_buff.data, 0);