chelsio/cxgb3/xgmac.c

54 	struct adapter *adap = mac->adapter;
57 	t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
61 	t3_read_reg(adap, ctrl);
65 		t3_set_reg_field(adap, ctrl, clear[i], 0);
99 	struct adapter *adap = mac->adapter;
102 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
103 	t3_read_reg(adap, A_XGM_RESET_CTRL + oft);	/* flush */
105 	t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
106 	t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
108 			 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
109 	t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX);
111 	if (uses_xaui(adap)) {
112 		if (adap->params.rev == 0) {
113 			t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
115 			if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
117 				CH_ERR(adap,
122 			t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
128 	t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
133 	if (is_10G(adap))
135 	else if (uses_xaui(adap))
139 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
140 	t3_read_reg(adap, A_XGM_RESET_CTRL + oft);	/* flush */
141 	if ((val & F_PCS_RESET_) && adap->params.rev) {
152 	struct adapter *adap = mac->adapter;
158 		t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
160 		t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
163 	t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0);
165 	t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0);
167 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
168 	t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
171 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
172 	store = t3_read_reg(adap, A_TP_TX_DROP_CFG_CH0 + idx);
177 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
178 	t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011);
182 	if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
184 		CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
189 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
190 	t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
193 	if (is_10G(adap))
195 	else if (uses_xaui(adap))
199 	t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
200 	t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
201 	if ((val & F_PCS_RESET_) && adap->params.rev) {
205 	t3_write_reg(adap, A_XGM_RX_CFG + oft,
210 	t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
211 	t3_write_reg(adap, A_TP_PIO_DATA, store);
214 		t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
216 		t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
219 	t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1);
222 	t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1);
303 	struct adapter *adap = mac->adapter;
306 	val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
309 	t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
332 	t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
333 	t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
350 	struct adapter *adap = mac->adapter;
362 	t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
364 	if (adap->params.rev >= T3_REV_B2 &&
365 	    (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
367 		v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
368 		t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
371 		reg = adap->params.rev == T3_REV_B2 ?
375 		if (t3_wait_op_done(adap, reg + mac->offset,
377 			t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
381 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
384 		t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
387 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
397 	v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
404 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
407 	thres = (adap->params.vpd.cclk * 1000) / 15625;
409 	if (is_10G(adap))
413 	ipg = (adap->params.rev == T3_REV_C) ? 0 : 1;
414 	t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
418 	if (adap->params.rev > 0) {
419 		divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
420 		t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
423 	t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
431 	struct adapter *adap = mac->adapter;
448 		t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
452 	val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
456 		    G_RXMAXPKTSIZE(t3_read_reg(adap,
460 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
462 	t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
470 	struct adapter *adap = mac->adapter;
475 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
476 		t3_write_reg(adap, A_TP_PIO_DATA,
477 			     adap->params.rev == T3_REV_C ?
479 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
480 		t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx,
481 				 adap->params.rev == T3_REV_C ? 0 : 1 << idx);
483 		t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
485 		t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
487 		mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
489 		mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
494 		mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
502 		t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
508 	struct adapter *adap = mac->adapter;
511 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
520 		t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
521 		if (is_10G(adap))
523 		else if (uses_xaui(adap))
534 	struct adapter *adap = mac->adapter;
544 		tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
548 			t3_write_reg(adap, A_TP_PIO_ADDR,
550 			tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
579 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
580 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
581 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
582 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */