chelsio/cxgb3/xgmac.c

41 static inline int macidx(const struct cmac *mac)
43 	return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
46 static void xaui_serdes_reset(struct cmac *mac)
54 	struct adapter *adap = mac->adapter;
55 	u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
57 	t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
70 void t3b_pcs_reset(struct cmac *mac)
72 	t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
75 	t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
79 int t3_mac_reset(struct cmac *mac)
99 	struct adapter *adap = mac->adapter;
100 	unsigned int oft = mac->offset;
119 				       macidx(mac));
125 			xaui_serdes_reset(mac);
143 		t3b_pcs_reset(mac);
146 	memset(&mac->stats, 0, sizeof(mac->stats));
150 static int t3b2_mac_reset(struct cmac *mac)
152 	struct adapter *adap = mac->adapter;
153 	unsigned int oft = mac->offset, store;
154 	int idx = macidx(mac);
157 	if (!macidx(mac))
185 		       macidx(mac));
203 		t3b_pcs_reset(mac);
230 static void set_addr_filter(struct cmac *mac, int idx, const u8 * addr)
233 	unsigned int oft = mac->offset + idx * 8;
238 	t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
239 	t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
243 int t3_mac_set_address(struct cmac *mac, unsigned int idx, const u8 addr[6])
245 	if (idx >= mac->nucast)
247 	set_addr_filter(mac, idx, addr);
256 int t3_mac_set_num_ucast(struct cmac *mac, int n)
260 	mac->nucast = n;
264 void t3_mac_disable_exact_filters(struct cmac *mac)
266 	unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;
269 		u32 v = t3_read_reg(mac->adapter, reg);
270 		t3_write_reg(mac->adapter, reg, v);
272 	t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1);	/* flush */
275 void t3_mac_enable_exact_filters(struct cmac *mac)
277 	unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;
280 		u32 v = t3_read_reg(mac->adapter, reg);
281 		t3_write_reg(mac->adapter, reg, v);
283 	t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1);	/* flush */
300 int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev)
303 	struct adapter *adap = mac->adapter;
304 	unsigned int oft = mac->offset;
315 		int exact_addr_idx = mac->nucast;
320 				set_addr_filter(mac, exact_addr_idx++,
345 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
350 	struct adapter *adap = mac->adapter;
362 	t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
365 	    (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
366 		t3_mac_disable_exact_filters(mac);
367 		v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
368 		t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
375 		if (t3_wait_op_done(adap, reg + mac->offset,
377 			t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
378 			t3_mac_enable_exact_filters(mac);
381 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
384 		t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
385 		t3_mac_enable_exact_filters(mac);
387 		t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
397 	v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
404 	t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
414 	t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
420 		t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
423 	t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
428 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
431 	struct adapter *adap = mac->adapter;
432 	unsigned int oft = mac->offset;
467 int t3_mac_enable(struct cmac *mac, int which)
469 	int idx = macidx(mac);
470 	struct adapter *adap = mac->adapter;
471 	unsigned int oft = mac->offset;
472 	struct mac_stats *s = &mac->stats;
486 		mac->tx_mcnt = s->tx_frames;
487 		mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
489 		mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
492 		mac->rx_mcnt = s->rx_frames;
493 		mac->rx_pause = s->rx_pause;
494 		mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
497 		mac->rx_ocnt = s->rx_fifo_ovfl;
498 		mac->txen = F_TXEN;
499 		mac->toggle_cnt = 0;
506 int t3_mac_disable(struct cmac *mac, int which)
508 	struct adapter *adap = mac->adapter;
511 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
512 		mac->txen = 0;
517 		t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
520 		t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
527 		t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
532 int t3b2_mac_watchdog_task(struct cmac *mac)
534 	struct adapter *adap = mac->adapter;
535 	struct mac_stats *s = &mac->stats;
542 	tx_tcnt = mac->tx_tcnt;	/* If tx_mcnt is progressing ignore tx_tcnt */
543 	if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) {
546 					       	mac->offset)));
549 				     A_TP_TX_DROP_CNT_CH0 + macidx(mac));
556 		mac->toggle_cnt = 0;
560 	if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
561 		if (mac->toggle_cnt > 4) {
569 		mac->toggle_cnt = 0;
574 	mac->tx_tcnt = tx_tcnt;
575 	mac->tx_xcnt = tx_xcnt;
576 	mac->tx_mcnt = s->tx_frames;
577 	mac->rx_pause = s->rx_pause;
579 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
580 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
581 		t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
582 		t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
583 		mac->toggle_cnt++;
585 		t3b2_mac_reset(mac);
586 		mac->toggle_cnt = 0;
598 const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
600 #define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
601 #define RMON_UPDATE(mac, name, reg) \
602 	(mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
603 #define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
604 	(mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
605 			     ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
609 	RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
610 	RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
611 	RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
612 	RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
613 	RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
614 	RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
615 	RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
616 	RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);
617 	RMON_UPDATE(mac, rx_symbol_errs, RX_SYM_CODE_ERR_FRAMES);
619 	RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
621 	v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
622 	if (mac->adapter->params.rev == T3_REV_B2)
624 	mac->stats.rx_too_long += v;
626 	RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
627 	RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
628 	RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
629 	RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES);
630 	RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES);
631 	RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES);
632 	RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES);
634 	RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH);
635 	RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH);
636 	RMON_UPDATE(mac, tx_mcast_frames, TX_MCAST);
637 	RMON_UPDATE(mac, tx_bcast_frames, TX_BCAST);
638 	RMON_UPDATE(mac, tx_pause, TX_PAUSE);
640 	RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES);
642 	RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES);
643 	RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES);
644 	RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES);
645 	RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES);
646 	RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES);
647 	RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES);
648 	RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES);
651 	t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);
652 	v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
653 	lo = (u32) mac->stats.rx_cong_drops;
654 	mac->stats.rx_cong_drops += (u64) (v - lo);
656 	return &mac->stats;