Lines Matching refs:adapter
38 static void t3_port_intr_clear(struct adapter *adapter, int idx);
42 * @adapter: the adapter performing the operation
56 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
60 u32 val = t3_read_reg(adapter, reg);
76 * @adapter: the adapter to program
85 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
89 t3_write_reg(adapter, p->reg_addr + offset, p->val);
96 * @adapter: the adapter to program
104 void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
107 u32 v = t3_read_reg(adapter, addr) & ~mask;
109 t3_write_reg(adapter, addr, v | val);
110 t3_read_reg(adapter, addr); /* flush */
115 * @adap: the adapter
125 static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
153 struct adapter *adap = mc7->adapter;
197 static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
214 struct adapter *adapter = pi->adapter;
218 mutex_lock(&adapter->mdio_lock);
219 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
220 t3_write_reg(adapter, A_MI1_ADDR, addr);
221 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
222 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
224 ret = t3_read_reg(adapter, A_MI1_DATA);
225 mutex_unlock(&adapter->mdio_lock);
233 struct adapter *adapter = pi->adapter;
237 mutex_lock(&adapter->mdio_lock);
238 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
239 t3_write_reg(adapter, A_MI1_ADDR, addr);
240 t3_write_reg(adapter, A_MI1_DATA, val);
241 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
242 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
243 mutex_unlock(&adapter->mdio_lock);
257 static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr,
262 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
263 t3_write_reg(adapter, A_MI1_ADDR, addr);
264 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
265 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
266 return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
277 struct adapter *adapter = pi->adapter;
280 mutex_lock(&adapter->mdio_lock);
281 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
283 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
284 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
287 ret = t3_read_reg(adapter, A_MI1_DATA);
289 mutex_unlock(&adapter->mdio_lock);
297 struct adapter *adapter = pi->adapter;
300 mutex_lock(&adapter->mdio_lock);
301 ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
303 t3_write_reg(adapter, A_MI1_DATA, val);
304 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
305 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
308 mutex_unlock(&adapter->mdio_lock);
549 int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
604 * @adapter: the adapter
609 int t3_seeprom_wp(struct adapter *adapter, int enable)
615 ret = pci_write_vpd_any(adapter->pdev, EEPROM_STAT_ADDR, sizeof(u32),
641 * @adapter: adapter to read
646 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
656 ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
661 ret = pci_read_vpd(adapter->pdev, addr, sizeof(vpd), &vpd);
683 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
684 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
685 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
726 * @adapter: the adapter
735 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
742 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
744 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
745 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
747 *valp = t3_read_reg(adapter, A_SF_DATA);
753 * @adapter: the adapter
762 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
767 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
769 t3_write_reg(adapter, A_SF_DATA, val);
770 t3_write_reg(adapter, A_SF_OP,
772 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
777 * @adapter: the adapter
783 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
789 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
790 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
803 * @adapter: the adapter
814 static int t3_read_flash(struct adapter *adapter, unsigned int addr,
824 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
825 (ret = sf1_read(adapter, 1, 1, data)) != 0)
829 ret = sf1_read(adapter, 4, nwords > 1, data);
840 * @adapter: the adapter
848 static int t3_write_flash(struct adapter *adapter, unsigned int addr,
860 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
861 (ret = sf1_write(adapter, 4, 1, val)) != 0)
869 ret = sf1_write(adapter, c, c != left, val);
873 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
877 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
888 * @adapter: the adapter
893 int t3_get_tp_version(struct adapter *adapter, u32 *vers)
898 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
899 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
904 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
911 * @adapter: the adapter
915 int t3_check_tpsram_version(struct adapter *adapter)
921 if (adapter->params.rev == T3_REV_A)
925 ret = t3_get_tp_version(adapter, &vers);
935 CH_ERR(adapter, "found wrong TP version (%u.%u), "
945 * @adapter: the adapter
949 * Checks if an adapter's tp sram is compatible with the driver.
952 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram,
963 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
978 * @adapter: the adapter
983 int t3_get_fw_version(struct adapter *adapter, u32 *vers)
985 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
990 * @adapter: the adapter
992 * Checks if an adapter's FW is compatible with the driver. Returns 0
995 int t3_check_fw_version(struct adapter *adapter)
1001 ret = t3_get_fw_version(adapter, &vers);
1013 CH_WARN(adapter, "found old FW minor version(%u.%u), "
1017 CH_WARN(adapter, "found newer FW version(%u.%u), "
1027 * @adapter: the adapter
1033 static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end)
1038 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
1039 (ret = sf1_write(adapter, 4, 0,
1041 (ret = flash_wait_op(adapter, 5, 500)) != 0)
1050 * @adapter: the adapter
1059 int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size)
1074 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1079 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1087 ret = t3_write_flash(adapter, addr, chunk_size, fw_data);
1096 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data);
1099 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1108 * @adap: the adapter
1115 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
1140 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG);
1141 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1145 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH);
1146 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0);
1148 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW);
1149 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0);
1159 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
1162 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high);
1163 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low);
1168 * @adapter: the adapter
1175 void t3_link_changed(struct adapter *adapter, int port_id)
1178 struct port_info *pi = adap2pinfo(adapter, port_id);
1189 t3_xgm_intr_enable(adapter, port_id);
1191 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1194 status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
1211 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1212 uses_xaui(adapter)) {
1215 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1228 t3_os_link_changed(adapter, port_id, link_ok && !pi->link_fault,
1232 void t3_link_fault(struct adapter *adapter, int port_id)
1234 struct port_info *pi = adap2pinfo(adapter, port_id);
1243 if (adapter->params.rev > 0 && uses_xaui(adapter))
1244 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0);
1246 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
1251 link_fault = t3_read_reg(adapter,
1267 t3_os_link_fault(adapter, port_id, 0);
1274 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1281 t3_os_link_fault(adapter, port_id, link_ok);
1332 * @adapter: the adapter
1333 * @ports: bitmap of adapter ports to operate on
1338 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on)
1340 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1354 * @adapter: the adapter that generated the interrupt
1367 static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
1373 unsigned int status = t3_read_reg(adapter, reg) & mask;
1380 CH_ALERT(adapter, "%s (0x%x)\n",
1384 CH_WARN(adapter, "%s (0x%x)\n",
1390 t3_write_reg(adapter, reg, status);
1455 static void pci_intr_handler(struct adapter *adapter)
1483 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1484 pcix1_intr_info, adapter->irq_stats))
1485 t3_fatal_err(adapter);
1491 static void pcie_intr_handler(struct adapter *adapter)
1513 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1514 CH_ALERT(adapter, "PEX error code 0x%x\n",
1515 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1517 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1518 pcie_intr_info, adapter->irq_stats))
1519 t3_fatal_err(adapter);
1525 static void tp_intr_handler(struct adapter *adapter)
1541 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1542 adapter->params.rev < T3_REV_C ?
1544 t3_fatal_err(adapter);
1550 static void cim_intr_handler(struct adapter *adapter)
1580 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff,
1582 t3_fatal_err(adapter);
1588 static void ulprx_intr_handler(struct adapter *adapter)
1602 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1604 t3_fatal_err(adapter);
1610 static void ulptx_intr_handler(struct adapter *adapter)
1621 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1622 ulptx_intr_info, adapter->irq_stats))
1623 t3_fatal_err(adapter);
1638 static void pmtx_intr_handler(struct adapter *adapter)
1651 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
1653 t3_fatal_err(adapter);
1668 static void pmrx_intr_handler(struct adapter *adapter)
1681 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
1683 t3_fatal_err(adapter);
1689 static void cplsw_intr_handler(struct adapter *adapter)
1701 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
1703 t3_fatal_err(adapter);
1709 static void mps_intr_handler(struct adapter *adapter)
1716 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
1718 t3_fatal_err(adapter);
1728 struct adapter *adapter = mc7->adapter;
1729 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1733 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
1735 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1736 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1737 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1738 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1743 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
1745 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1746 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1747 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1748 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1753 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
1760 if (adapter->params.rev > 0)
1761 addr = t3_read_reg(adapter,
1764 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
1769 t3_fatal_err(adapter);
1771 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1779 static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1828 int t3_phy_intr_handler(struct adapter *adapter)
1830 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1832 for_each_port(adapter, i) {
1833 struct port_info *p = adap2pinfo(adapter, i);
1838 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) {
1842 t3_link_changed(adapter, i);
1846 t3_os_phymod_changed(adapter, i);
1850 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1857 int t3_slow_intr_handler(struct adapter *adapter)
1859 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1861 cause &= adapter->slow_intr_mask;
1865 if (is_pcie(adapter))
1866 pcie_intr_handler(adapter);
1868 pci_intr_handler(adapter);
1871 t3_sge_err_intr_handler(adapter);
1873 mc7_intr_handler(&adapter->pmrx);
1875 mc7_intr_handler(&adapter->pmtx);
1877 mc7_intr_handler(&adapter->cm);
1879 cim_intr_handler(adapter);
1881 tp_intr_handler(adapter);
1883 ulprx_intr_handler(adapter);
1885 ulptx_intr_handler(adapter);
1887 pmrx_intr_handler(adapter);
1889 pmtx_intr_handler(adapter);
1891 cplsw_intr_handler(adapter);
1893 mps_intr_handler(adapter);
1895 t3_mc5_intr_handler(&adapter->mc5);
1897 mac_intr_handler(adapter, 0);
1899 mac_intr_handler(adapter, 1);
1901 t3_os_ext_intr_handler(adapter);
1904 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1905 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1909 static unsigned int calc_gpio_intr(struct adapter *adap)
1922 * @adapter: the adapter whose interrupts should be enabled
1928 void t3_intr_enable(struct adapter *adapter)
1945 adapter->slow_intr_mask = PL_INTR_MASK;
1947 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1948 t3_write_reg(adapter, A_TP_INT_ENABLE,
1949 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
1951 if (adapter->params.rev > 0) {
1952 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1954 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1958 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1959 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1962 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
1964 if (is_pcie(adapter))
1965 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1967 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1968 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1969 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1974 * @adapter: the adapter whose interrupts should be disabled
1979 void t3_intr_disable(struct adapter *adapter)
1981 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
1982 t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1983 adapter->slow_intr_mask = 0;
1988 * @adapter: the adapter whose interrupts should be cleared
1992 void t3_intr_clear(struct adapter *adapter)
2015 for_each_port(adapter, i)
2016 t3_port_intr_clear(adapter, i);
2019 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
2021 if (is_pcie(adapter))
2022 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
2023 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
2024 t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
2027 void t3_xgm_intr_enable(struct adapter *adapter, int idx)
2029 struct port_info *pi = adap2pinfo(adapter, idx);
2031 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset,
2035 void t3_xgm_intr_disable(struct adapter *adapter, int idx)
2037 struct port_info *pi = adap2pinfo(adapter, idx);
2039 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset,
2045 * @adapter: associated adapter
2049 * adapter port.
2051 void t3_port_intr_enable(struct adapter *adapter, int idx)
2053 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2055 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK);
2056 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2062 * @adapter: associated adapter
2066 * adapter port.
2068 void t3_port_intr_disable(struct adapter *adapter, int idx)
2070 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2072 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0);
2073 t3_read_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx)); /* flush */
2079 * @adapter: associated adapter
2083 * adapter port.
2085 static void t3_port_intr_clear(struct adapter *adapter, int idx)
2087 struct cphy *phy = &adap2pinfo(adapter, idx)->phy;
2089 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff);
2090 t3_read_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx)); /* flush */
2098 * @adapter: the adapter
2105 static int t3_sge_write_context(struct adapter *adapter, unsigned int id,
2115 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2116 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2117 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff);
2118 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2120 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
2121 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
2122 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
2123 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
2125 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2127 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2133 * @adap: the adapter
2142 static int clear_sge_ctxt(struct adapter *adap, unsigned int id,
2161 * @adapter: the adapter to configure
2176 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
2185 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2189 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
2191 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
2194 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr);
2196 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2200 return t3_sge_write_context(adapter, id, F_EGRESS);
2205 * @adapter: the adapter to configure
2219 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
2226 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2230 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr);
2232 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
2235 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
2238 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2241 return t3_sge_write_context(adapter, id, F_FREELIST);
2246 * @adapter: the adapter to configure
2259 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
2267 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2271 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2273 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2277 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2279 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2280 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
2285 * @adapter: the adapter to configure
2298 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
2304 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2308 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2309 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr);
2311 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2315 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2317 return t3_sge_write_context(adapter, id, F_CQ);
2322 * @adapter: the adapter
2329 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable)
2331 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2334 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2335 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2336 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2337 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2338 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2339 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2341 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2347 * @adapter: the adapter
2353 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id)
2355 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2358 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2359 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2360 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2361 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2362 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2363 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2365 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2371 * @adapter: the adapter
2377 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id)
2379 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2382 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2383 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2384 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2385 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2386 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2387 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2389 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2395 * @adapter: the adapter
2401 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id)
2403 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2406 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2407 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2408 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2409 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2410 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2411 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2413 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2419 * @adapter: the adapter
2428 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
2433 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2436 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2437 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2439 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2444 if (adapter->params.rev > 0)
2447 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2449 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
2453 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2460 * @adapter: the adapter
2470 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
2484 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2489 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2495 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2500 * @adap: the adapter
2505 void t3_tp_set_offload_mode(struct adapter *adap, int enable)
2535 * @adap: the adapter
2541 static void partition_mem(struct adapter *adap, const struct tp_params *p)
2599 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,
2606 static void tp_config(struct adapter *adap, const struct tp_params *p)
2665 * @adap: the adapter to set
2671 static void tp_set_timers(struct adapter *adap, unsigned int core_clk)
2709 * @adap: the adapter
2715 static int t3_tp_set_coalescing_size(struct adapter *adap,
2740 * @adap: the adapter
2746 static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)
2822 * @adap: the adapter
2832 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
2867 * @adap: the adapter
2872 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)
2889 static void ulp_config(struct adapter *adap, const struct tp_params *p)
2905 * @adap: the adapter
2910 int t3_set_proto_sram(struct adapter *adap, const u8 *data)
2931 void t3_config_trace_filter(struct adapter *adapter,
2953 tp_wr_indirect(adapter, addr++, key[0]);
2954 tp_wr_indirect(adapter, addr++, mask[0]);
2955 tp_wr_indirect(adapter, addr++, key[1]);
2956 tp_wr_indirect(adapter, addr++, mask[1]);
2957 tp_wr_indirect(adapter, addr++, key[2]);
2958 tp_wr_indirect(adapter, addr++, mask[2]);
2959 tp_wr_indirect(adapter, addr++, key[3]);
2960 tp_wr_indirect(adapter, addr, mask[3]);
2961 t3_read_reg(adapter, A_TP_PIO_DATA);
2966 * @adap: the adapter
2972 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)
3008 static int tp_init(struct adapter *adap, const struct tp_params *p)
3033 static void chan_init_hw(struct adapter *adap, unsigned int chan_map)
3063 static int calibrate_xgm(struct adapter *adapter)
3065 if (uses_xaui(adapter)) {
3069 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3070 t3_read_reg(adapter, A_XGM_XAUI_IMP);
3072 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3074 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3079 CH_ERR(adapter, "MAC calibration failed\n");
3082 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3084 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3090 static void calibrate_xgm_t3b(struct adapter *adapter)
3092 if (!uses_xaui(adapter)) {
3093 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3095 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
3096 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
3098 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3100 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
3101 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
3120 static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val)
3122 t3_write_reg(adapter, addr, val);
3123 t3_read_reg(adapter, addr); /* flush */
3124 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3126 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
3145 struct adapter *adapter = mc7->adapter;
3151 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3156 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3157 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3161 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3162 t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3164 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3166 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3172 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3178 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3180 t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3183 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3188 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3189 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
3190 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
3191 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3195 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3196 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);
3200 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3201 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3202 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3203 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
3205 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
3206 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3213 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3215 t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3217 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);
3218 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3219 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3220 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3222 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3223 t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3228 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3231 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3236 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3243 static void config_pcie(struct adapter *adap)
3309 int t3_init_hw(struct adapter *adapter, u32 fw_params)
3312 const struct vpd_params *vpd = &adapter->params.vpd;
3314 if (adapter->params.rev > 0)
3315 calibrate_xgm_t3b(adapter);
3316 else if (calibrate_xgm(adapter))
3320 partition_mem(adapter, &adapter->params.tp);
3322 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3323 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3324 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3325 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3326 adapter->params.mc5.nfilters,
3327 adapter->params.mc5.nroutes))
3331 if (clear_sge_ctxt(adapter, i, F_CQ))
3335 if (tp_init(adapter, &adapter->params.tp))
3338 t3_tp_set_coalescing_size(adapter,
3339 min(adapter->params.sge.max_pkt_size,
3341 t3_tp_set_max_rxsize(adapter,
3342 min(adapter->params.sge.max_pkt_size, 16384U));
3343 ulp_config(adapter, &adapter->params.tp);
3345 if (is_pcie(adapter))
3346 config_pcie(adapter);
3348 t3_set_reg_field(adapter, A_PCIX_CFG, 0,
3351 if (adapter->params.rev == T3_REV_C)
3352 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
3355 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3356 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3357 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3358 chan_init_hw(adapter, adapter->params.chan_map);
3359 t3_sge_init(adapter, &adapter->params.sge);
3360 t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN);
3362 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter));
3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3365 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3367 t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3372 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3374 CH_ERR(adapter, "uP initialization timed out\n");
3385 * @adapter: the adapter
3391 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
3396 if (pci_is_pcie(adapter->pdev)) {
3400 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3405 pci_mode = t3_read_reg(adapter, A_PCIX_MODE);
3462 static void mc7_prep(struct adapter *adapter, struct mc7 *mc7,
3467 mc7->adapter = adapter;
3470 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3475 static void mac_prep(struct cmac *mac, struct adapter *adapter, int index)
3479 mac->adapter = adapter;
3480 pci_read_config_word(adapter->pdev, 0x2, &devid);
3482 if (devid == 0x37 && !adapter->params.vpd.xauicfg[1])
3487 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
3488 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3489 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
3490 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3495 static void early_hw_init(struct adapter *adapter,
3498 u32 val = V_PORTSPEED(is_10G(adapter) ? 3 : 2);
3500 mi1_init(adapter, ai);
3501 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3502 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3503 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3505 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3506 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
3508 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3512 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3513 t3_read_reg(adapter, A_XGM_PORT_CFG);
3516 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3517 t3_read_reg(adapter, A_XGM_PORT_CFG);
3518 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3519 t3_read_reg(adapter, A_XGM_PORT_CFG);
3523 * Reset the adapter.
3527 int t3_reset_adapter(struct adapter *adapter)
3530 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
3534 pci_save_state(adapter->pdev);
3535 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3543 pci_read_config_word(adapter->pdev, 0x00, &devid);
3552 pci_restore_state(adapter->pdev);
3556 static int init_parity(struct adapter *adap)
3587 * Initialize adapter SW state for the various HW modules, set initial values
3588 * for some adapter tunables, take PHYs out of reset, and initialize the MDIO
3591 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
3597 get_pci_mode(adapter, &adapter->params.pci);
3599 adapter->params.info = ai;
3600 adapter->params.nports = ai->nports0 + ai->nports1;
3601 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1);
3602 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3604 * We used to only run the "adapter check task" once a second if
3609 * adapter state once a second ...
3611 adapter->params.linkpoll_period = 10;
3612 adapter->params.stats_update_period = is_10G(adapter) ?
3614 adapter->params.pci.vpd_cap_addr =
3615 pci_find_capability(adapter->pdev, PCI_CAP_ID_VPD);
3616 if (!adapter->params.pci.vpd_cap_addr)
3618 ret = get_vpd_params(adapter, &adapter->params.vpd);
3622 if (reset && t3_reset_adapter(adapter))
3625 t3_sge_prep(adapter, &adapter->params.sge);
3627 if (adapter->params.vpd.mclk) {
3628 struct tp_params *p = &adapter->params.tp;
3630 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
3631 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
3632 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
3634 p->nchan = adapter->params.chan_map == 3 ? 2 : 1;
3635 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
3636 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
3637 p->cm_size = t3_mc7_size(&adapter->cm);
3641 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
3645 adapter->params.rev > 0 ? 12 : 6;
3648 adapter->params.offload = t3_mc7_size(&adapter->pmrx) &&
3649 t3_mc7_size(&adapter->pmtx) &&
3650 t3_mc7_size(&adapter->cm);
3652 if (is_offload(adapter)) {
3653 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
3654 adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
3656 adapter->params.mc5.nroutes = 0;
3657 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
3659 init_mtus(adapter->params.mtus);
3660 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3663 early_hw_init(adapter, ai);
3664 ret = init_parity(adapter);
3668 for_each_port(adapter, i) {
3671 struct port_info *p = adap2pinfo(adapter, i);
3673 while (!adapter->params.vpd.port_type[++j])
3676 pti = &port_types[adapter->params.vpd.port_type[j]];
3678 CH_ALERT(adapter, "Invalid port type index %d\n",
3679 adapter->params.vpd.port_type[j]);
3683 p->phy.mdio.dev = adapter->port[i];
3684 ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3688 mac_prep(&p->mac, adapter, j);
3695 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3696 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3698 eth_hw_addr_set(adapter->port[i], hw_addr);
3704 * changes, schedule a scan of the adapter links at least
3708 adapter->params.linkpoll_period > 10)
3709 adapter->params.linkpoll_period = 10;
3715 void t3_led_ready(struct adapter *adapter)
3717 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
3721 int t3_replay_prep_adapter(struct adapter *adapter)
3723 const struct adapter_info *ai = adapter->params.info;
3727 early_hw_init(adapter, ai);
3728 ret = init_parity(adapter);
3732 for_each_port(adapter, i) {
3734 struct port_info *p = adap2pinfo(adapter, i);
3736 while (!adapter->params.vpd.port_type[++j])
3739 pti = &port_types[adapter->params.vpd.port_type[j]];
3740 ret = pti->phy_prep(&p->phy, adapter, p->phy.mdio.prtad, NULL);