chelsio/cxgb3/t3_hw.c

115  *	@adap: the adapter
125 static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
130 		t3_write_reg(adap, addr_reg, start_idx);
131 		*vals++ = t3_read_reg(adap, data_reg);
153 	struct adapter *adap = mc7->adapter;
167 			t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
168 			t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
169 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
171 				val = t3_read_reg(adap,
176 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
178 				val64 = t3_read_reg(adap,
197 static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
199 	u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
202 	t3_write_reg(adap, A_MI1_CFG, val);
1108  *      @adap: the adapter
1115 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
1120 	if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1124 		t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1125 		ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1128 			*valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1779 static int mac_intr_handler(struct adapter *adap, unsigned int idx)
1781 	struct cmac *mac = &adap2pinfo(adap, idx)->mac;
1788 	u32 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) &
1793 		CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
1797 		CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
1810 		t3_set_reg_field(adap,
1815 		t3_os_link_fault_handler(adap, idx);
1819 		t3_fatal_err(adap);
1821 	t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1909 static unsigned int calc_gpio_intr(struct adapter *adap)
1913 	for_each_port(adap, i)
1914 		if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) &&
1915 		    adapter_info(adap)->gpio_intr[i])
1916 			gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i];
2133  *	@adap: the adapter
2142 static int clear_sge_ctxt(struct adapter *adap, unsigned int id,
2145 	t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
2146 	t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
2147 	t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
2148 	t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
2149 	t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff);
2150 	t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff);
2151 	t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff);
2152 	t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff);
2153 	t3_write_reg(adap, A_SG_CONTEXT_CMD,
2155 	return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2500  *	@adap: the adapter
2505 void t3_tp_set_offload_mode(struct adapter *adap, int enable)
2507 	if (is_offload(adap) || !enable)
2508 		t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2529 #define mem_region(adap, start, size, reg) \
2530 	t3_write_reg((adap), A_ ## reg, (start)); \
2535  *	@adap: the adapter
2541 static void partition_mem(struct adapter *adap, const struct tp_params *p)
2543 	unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
2546 	if (adap->params.rev > 0) {
2559 	t3_write_reg(adap, A_TP_PMM_SIZE,
2562 	t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2563 	t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2564 	t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2565 	t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2568 	t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2569 	t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2570 	t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2576 	t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2579 	mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
2580 	mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
2581 	t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2583 	mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
2584 	mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
2585 	mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
2586 	mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
2589 	t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2590 	t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2593 	m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
2594 	    adap->params.mc5.nfilters - adap->params.mc5.nroutes;
2596 		adap->params.mc5.nservers += m - tids;
2599 static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr,
2602 	t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2603 	t3_write_reg(adap, A_TP_PIO_DATA, val);
2606 static void tp_config(struct adapter *adap, const struct tp_params *p)
2608 	t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2611 	t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2614 	t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2618 	t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
2620 	t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2621 	t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2622 	t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2623 			 adap->params.rev > 0 ? F_ENABLEESND :
2626 	t3_set_reg_field(adap, A_TP_PC_CONFIG,
2630 	t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
2633 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2634 	t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2636 	if (adap->params.rev > 0) {
2637 		tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2638 		t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
2640 		t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2641 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
2643 		t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2645 	if (adap->params.rev == T3_REV_C)
2646 		t3_set_reg_field(adap, A_TP_PC_CONFIG,
2650 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2651 	t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2652 	t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2653 	t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2665  *	@adap: the adapter to set
2671 static void tp_set_timers(struct adapter *adap, unsigned int core_clk)
2678 	t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2681 	t3_write_reg(adap, A_TP_DACK_TIMER,
2683 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2684 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2685 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2686 	t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2687 	t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2694 	t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS);
2695 	t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2696 	t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2697 	t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2698 	t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2699 	t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2700 	t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2701 	t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2702 	t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2709  *	@adap: the adapter
2715 static int t3_tp_set_coalescing_size(struct adapter *adap,
2723 	val = t3_read_reg(adap, A_TP_PARA_REG3);
2731 		t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2734 	t3_write_reg(adap, A_TP_PARA_REG3, val);
2740  *	@adap: the adapter
2746 static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size)
2748 	t3_write_reg(adap, A_TP_PARA_REG7,
2822  *	@adap: the adapter
2832 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
2850 		t3_write_reg(adap, A_TP_MTU_TABLE,
2859 			t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2867  *	@adap: the adapter
2872 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps)
2874 	t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *) tps,
2878 #define ulp_region(adap, name, start, len) \
2879 	t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2880 	t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2884 #define ulptx_region(adap, name, start, len) \
2885 	t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2886 	t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2889 static void ulp_config(struct adapter *adap, const struct tp_params *p)
2893 	ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
2894 	ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
2895 	ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
2896 	ulp_region(adap, STAG, m, p->chan_rx_size / 4);
2897 	ulp_region(adap, RQ, m, p->chan_rx_size / 4);
2898 	ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
2899 	ulp_region(adap, PBL, m, p->chan_rx_size / 4);
2900 	t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
2905  *	@adap: the adapter
2910 int t3_set_proto_sram(struct adapter *adap, const u8 *data)
2916 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++));
2917 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++));
2918 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++));
2919 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++));
2920 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++));
2922 		t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
2923 		if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
2926 	t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0);
2966  *	@adap: the adapter
2972 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched)
2975 	unsigned int clk = adap->params.vpd.cclk * 1000;
2997 	t3_write_reg(adap, A_TP_TM_PIO_ADDR,
2999 	v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3004 	t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3008 static int tp_init(struct adapter *adap, const struct tp_params *p)
3012 	tp_config(adap, p);
3013 	t3_set_vlan_accel(adap, 3, 0);
3015 	if (is_offload(adap)) {
3016 		tp_set_timers(adap, adap->params.vpd.cclk * 1000);
3017 		t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3018 		busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
3021 			CH_ERR(adap, "TP initialization timed out\n");
3025 		t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3033 static void chan_init_hw(struct adapter *adap, unsigned int chan_map)
3038 		t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
3039 		t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
3040 		t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |
3043 		t3_write_reg(adap, A_PM1_TX_CFG,
3046 		t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
3047 		t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
3048 		t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3050 		t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3053 		t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3054 		t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
3055 		t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3058 			t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3243 static void config_pcie(struct adapter *adap)
3262 	pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);
3265 	pci_read_config_word(adap->pdev, 0x2, &devid);
3267 		pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
3273 	pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);
3275 	fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3276 	fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
3277 	    G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3278 	log2_width = fls(adap->params.pci.width) - 1;
3284 	if (adap->params.rev == 0)
3285 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3289 		t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3292 	t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3295 	t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3296 	t3_set_reg_field(adap, A_PCIE_CFG, 0,
3556 static int init_parity(struct adapter *adap)
3560 	if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
3564 		err = clear_sge_ctxt(adap, i, F_EGRESS);
3566 		err = clear_sge_ctxt(adap, i, F_EGRESS);
3568 		err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
3572 	t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
3575 			t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
3578 			err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,