chelsio/cxgb3/mc5.c

128 	struct adapter *adap = mc5->adapter;
135 	unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
143 	dbgi_wr_data3(adap, 0, 0, 0);
145 		if (mc5_write(adap, data_array_base + (i << addr_shift),
150 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
153 			t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
156 		if (mc5_write(adap, mask_array_base + (i << addr_shift),
166 	struct adapter *adap = mc5->adapter;
168 	t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
170 	t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
176 	t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
177 	t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
178 	t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
179 	t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
180 	t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
181 	t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
182 	t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
183 	t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
184 	t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
185 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
186 	t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
187 	t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
190 	t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
193 	dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
194 	if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
198 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
199 	if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
200 	    mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
206 			dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
208 			dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
210 			dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
212 		if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
217 	dbgi_wr_data3(adap, 1, 0, 0);
218 	if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
230 	struct adapter *adap = mc5->adapter;
232 	t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
233 		     adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
240 	t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
241 	t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
242 	t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
244 	t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
245 	t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
246 	t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
247 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
248 	t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
249 	t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
251 	t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
254 	t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
257 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
259 		if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
263 		if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
266 	dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
267 	if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
268 	    mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
269 	    mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
272 	dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
273 	if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
277 	dbgi_wr_data3(adap, 0xf0000000, 0, 0);
278 	if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
313 	struct adapter *adap = mc5->adapter;
322 	cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
324 	t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
325 	if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
326 		CH_ERR(adap, "TCAM reset timed out\n");
330 	t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
331 	t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
333 	t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
339 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
340 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
352 		CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
369 	struct adapter *adap = mc5->adapter;
370 	u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
373 		CH_ALERT(adap, "MC5 parity error\n");
378 		CH_ALERT(adap, "MC5 request queue parity error\n");
383 		CH_ALERT(adap, "MC5 dispatch queue parity error\n");
396 		t3_fatal_err(adap);
398 	t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);