chelsio/cxgb3/ael1002.c

86 	int err;
88 	for (err = 0; rv->mmd_addr && !err; rv++) {
90 			err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
93 			err = t3_mdio_change_bits(phy, rv->mmd_addr,
97 	return err;
115 	int i, err;
118 	err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
120 	if (err)
121 		return err;
125 		err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
126 		if (err)
127 			return err;
129 			err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
131 			if (err)
132 				return err;
143 	int err;
145 	err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
146 	if (!err)
147 		err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
150 	return err;
155 	int err;
157 	if ((err = ael1002_power_down(phy, 0)) ||
158 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
159 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
160 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
161 	    (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
162 	    (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
164 		return err;
181 		int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
184 		if (!err)
185 			err = t3_mdio_read(phy, MDIO_MMD_PCS,
187 		if (!err)
188 			err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
190 		if (err)
191 			return err;
302 	int i, err;
304 	err = set_phy_regs(phy, regs);
305 	if (err)
306 		return err;
311 		err = t3_get_edc_fw(phy, EDC_OPT_AEL2005,
313 	if (err)
314 		return err;
316 	for (i = 0; i <  EDC_OPT_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
317 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
320 	if (!err)
322 	return err;
336 	int i, err;
338 	err = set_phy_regs(phy, regs);
339 	if (!err && modtype == phy_modtype_twinax_long)
340 		err = set_phy_regs(phy, preemphasis);
341 	if (err)
342 		return err;
347 		err = t3_get_edc_fw(phy, EDC_TWX_AEL2005,
349 	if (err)
350 		return err;
352 	for (i = 0; i <  EDC_TWX_AEL2005_SIZE / sizeof(u16) && !err; i += 2)
353 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
356 	if (!err)
358 	return err;
378 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
379 	return err ? err : t3_phy_lasi_intr_enable(phy);
384 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
385 	return err ? err : t3_phy_lasi_intr_disable(phy);
390 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
391 	return err ? err : t3_phy_lasi_intr_clear(phy);
412 	int err;
415 	err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
417 	if (err)
418 		return err;
420 	err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
421 	if (err)
422 		return err;
426 	err = set_phy_regs(phy, regs0);
427 	if (err)
428 		return err;
432 	err = ael2005_get_module_type(phy, 0);
433 	if (err < 0)
434 		return err;
435 	phy->modtype = err;
437 	if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
438 		err = ael2005_setup_twinax_edc(phy, err);
440 		err = ael2005_setup_sr_edc(phy);
441 	if (err)
442 		return err;
444 	err = set_phy_regs(phy, regs1);
445 	if (err)
446 		return err;
450 		err = ael2005_intr_enable(phy);
451 	return err;
537 	int err;
539 	err = set_phy_regs(phy, regs);
541 	if (err)
542 		return err;
572 	int i, err;
575 	err = set_phy_regs(phy, uCclock40MHz);
577 	if (err)
578 		return err;
579 	err = set_phy_regs(phy, uCclockActivate);
581 	if (err)
582 		return err;
585 		err = t3_get_edc_fw(phy, EDC_TWX_AEL2020,
587 	if (err)
588 		return err;
590 	for (i = 0; i <  EDC_TWX_AEL2020_SIZE / sizeof(u16) && !err; i += 2)
591 		err = t3_mdio_write(phy, MDIO_MMD_PMAPMD,
595 	err = set_phy_regs(phy, uCactivate);
596 	if (!err)
598 	return err;
641 	int err, link_ok = 0;
644 	err = set_phy_regs(phy, regs);
645 	if (err)
646 		return err;
648 	err = get_link_status_r(phy, &link_ok, NULL, NULL, NULL);
649 	if (err)
650 		return err;
655 	err = t3_phy_lasi_intr_enable(phy);
656 	if (err)
657 		return err;
679 	int err;
682 	err = set_phy_regs(phy, regs);
683 	if (err)
684 		return err;
700 	int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_INTR, &stat);
701 	return err ? err : t3_phy_lasi_intr_clear(phy);
724 	int err;
728 	err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
730 	if (err)
731 		return err;
733 	err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 125);
734 	if (err)
735 		return err;
740 	err = set_phy_regs(phy, ael2020_reset_regs);
741 	if (err)
742 		return err;
745 	err = ael2020_get_module_type(phy, 0);
746 	if (err < 0)
747 		return err;
748 	phy->modtype = (u8)err;
749 	if (err == phy_modtype_twinax || err == phy_modtype_twinax_long)
750 		err = ael2020_setup_twinax_edc(phy, err);
752 		err = ael2020_setup_sr_edc(phy);
753 	if (err)
754 		return err;
758 		err = ael2005_intr_enable(phy);
759 	return err;
834 		int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
837 		if (!err)
838 			err = t3_mdio_read(phy, MDIO_MMD_PCS,
840 		if (!err)
841 			err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
843 		if (err)
844 			return err;