cavium/liquidio/cn68xx_device.c

31 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)
36 	lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
37 	dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",
38 		lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
45 		lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
46 		lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
47 		dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,
48 			lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
55 	lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
56 	dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",
57 		lio_pci_readq(oct, CN6XXX_DPI_CTL));
60 static int lio_cn68xx_soft_reset(struct octeon_device *oct)
62 	lio_cn6xxx_soft_reset(oct);
63 	lio_cn68xx_set_dpi_regs(oct);
68 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
70 	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
73 	pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);
76 	max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx));
77 	tx_pipe  = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
80 	octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);
87 	octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);
90 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)
92 	lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);
93 	lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);
94 	lio_cn6xxx_enable_error_reporting(oct);
96 	lio_cn6xxx_setup_global_input_regs(oct);
97 	lio_cn68xx_setup_pkt_ctl_regs(oct);
98 	lio_cn6xxx_setup_global_output_regs(oct);
103 	octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);
108 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct)
113 	pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val);
115 	pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val);
118 static int lio_is_210nv(struct octeon_device *oct)
120 	u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);
125 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct)
127 	struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
130 	if (octeon_map_pci_barx(oct, 0, 0))
133 	if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
134 		dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n",
136 		octeon_unmap_pci_barx(oct, 0);
142 	oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs;
143 	oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs;
145 	oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs;
146 	oct->fn_list.soft_reset = lio_cn68xx_soft_reset;
147 	oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs;
148 	oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index;
150 	oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup;
151 	oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write;
152 	oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read;
154 	oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt;
155 	oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt;
157 	oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues;
158 	oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues;
160 	lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list);
163 	if (lio_is_210nv(oct))
167 		       oct_get_config_info(oct, card_type);
169 		dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n",
173 		octeon_unmap_pci_barx(oct, 0);
174 		octeon_unmap_pci_barx(oct, 1);
178 	oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct);
180 	lio_cn68xx_vendor_message_fix(oct);