cavium/liquidio/cn23xx_pf_device.c

305 	u64 reg_val;
314 	reg_val =
319 		reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
322 		reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF;
326 	reg_val = reg_val |
330 	reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS);
334 	reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS);
338 			   reg_val);
368 		u64 reg_val = octeon_read_csr64(oct,
370 		while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
371 		       !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
373 			WRITE_ONCE(reg_val, octeon_read_csr64(
382 		WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
385 				   READ_ONCE(reg_val));
387 		WRITE_ONCE(reg_val, octeon_read_csr64(
389 		if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
404 	u64 intr_threshold, reg_val;
423 		reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
433 		reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS;
434 		reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
437 				   reg_val);
453 		reg_val =
456 		reg_val |= CN23XX_PKT_INPUT_CTL_MASK;
459 				   reg_val);
477 	u32 reg_val;
494 		reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
497 		reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;
500 		reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;
503 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
509 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
510 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
513 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
515 		reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
521 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
522 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
524 		reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
527 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);
630 	u32 reg_val;
654 		reg_val =
656 		reg_val |= CN23XX_PKT_OUTPUT_CTL_TENB;
658 				 reg_val);
662 		reg_val =
664 		reg_val |= CN23XX_PKT_OUTPUT_CTL_CENB;
666 				 reg_val);
790 	u64 reg_val;
800 			reg_val = octeon_read_csr64(
802 			reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
804 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
812 			reg_val = octeon_read_csr64(
815 			if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
816 				while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
817 				       !(reg_val &
820 					reg_val = octeon_read_csr64(
830 				reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
833 				    reg_val);
835 				reg_val = octeon_read_csr64(
837 				if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
844 			reg_val = octeon_read_csr64(
846 			reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
848 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
852 		u32 reg_val;
855 			reg_val = octeon_read_csr(
857 			reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
859 					 reg_val);