ethernet/cadence/macb_ptp.c

28 static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,
31 	if (bp->hw_dma_cap == HW_DMA_CAP_PTP)
34 	if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP)
44 	struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
49 	spin_lock_irqsave(&bp->tsu_clk_lock, flags);
51 	first = gem_readl(bp, TN);
53 	secl = gem_readl(bp, TSL);
54 	sech = gem_readl(bp, TSH);
55 	second = gem_readl(bp, TN);
63 		ts->tv_nsec = gem_readl(bp, TN);
65 		secl = gem_readl(bp, TSL);
66 		sech = gem_readl(bp, TSH);
71 	spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
80 	struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
88 	spin_lock_irqsave(&bp->tsu_clk_lock, flags);
91 	gem_writel(bp, TN, 0); /* clear to avoid overflow */
92 	gem_writel(bp, TSH, sech);
94 	gem_writel(bp, TSL, secl);
95 	gem_writel(bp, TN, ns);
97 	spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
102 static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
111 	spin_lock_irqsave(&bp->tsu_clk_lock, flags);
113 	gem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec->sub_ns) |
116 	gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
117 	spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
124 	struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
136 	incr_spec.sub_ns = bp->tsu_incr.sub_ns;
137 	incr_spec.ns = bp->tsu_incr.ns;
153 	gem_tsu_incr_set(bp, &incr_spec);
159 	struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
169 		gem_tsu_get_time(&bp->ptp_clock_info, &now, NULL);
172 		gem_tsu_set_time(&bp->ptp_clock_info,
177 		gem_writel(bp, TA, adj);
205 static void gem_ptp_init_timer(struct macb *bp)
210 	bp->tsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp->tsu_rate, &rem);
214 		bp->tsu_incr.sub_ns = div_u64(adj, bp->tsu_rate);
216 		bp->tsu_incr.sub_ns = 0;
220 static void gem_ptp_init_tsu(struct macb *bp)
228 	gem_tsu_set_time(&bp->ptp_clock_info, &ts);
231 	gem_tsu_incr_set(bp, &bp->tsu_incr);
233 	gem_writel(bp, TA, 0);
236 static void gem_ptp_clear_timer(struct macb *bp)
238 	bp->tsu_incr.sub_ns = 0;
239 	bp->tsu_incr.ns = 0;
241 	gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));
242 	gem_writel(bp, TI, GEM_BF(NSINCR, 0));
243 	gem_writel(bp, TA, 0);
246 static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,
259 	gem_tsu_get_time(&bp->ptp_clock_info, &tsu, NULL);
274 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb,
282 		desc_ptp = macb_ptp_desc(bp, desc);
285 			dev_warn_ratelimited(&bp->pdev->dev,
289 		gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
295 void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb,
303 		dev_warn_ratelimited(&bp->pdev->dev,
308 	desc_ptp = macb_ptp_desc(bp, desc);
311 		dev_warn_ratelimited(&bp->pdev->dev,
318 	gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
327 	struct macb *bp = netdev_priv(dev);
329 	bp->ptp_clock_info = gem_ptp_caps_template;
332 	bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
333 	bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
334 	gem_ptp_init_timer(bp);
335 	bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &dev->dev);
336 	if (IS_ERR(bp->ptp_clock)) {
338 			PTR_ERR(bp->ptp_clock));
339 		bp->ptp_clock = NULL;
341 	} else if (bp->ptp_clock == NULL) {
346 	spin_lock_init(&bp->tsu_clk_lock);
348 	gem_ptp_init_tsu(bp);
350 	dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
356 	struct macb *bp = netdev_priv(ndev);
358 	if (bp->ptp_clock)
359 		ptp_clock_unregister(bp->ptp_clock);
361 	gem_ptp_clear_timer(bp);
363 	dev_info(&bp->pdev->dev, "%s ptp clock unregistered.\n",
367 static int gem_ptp_set_ts_mode(struct macb *bp,
371 	gem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));
372 	gem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));
380 	struct macb *bp = netdev_priv(dev);
382 	*tstamp_config = bp->tstamp_config;
383 	if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
389 static void gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)
393 	reg_val = macb_readl(bp, NCR);
396 		macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));
398 		macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));
407 	struct macb *bp = netdev_priv(dev);
410 	if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
417 		gem_ptp_set_one_step_sync(bp, 1);
421 		gem_ptp_set_one_step_sync(bp, 0);
446 		regval = macb_readl(bp, NCR);
447 		macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));
459 	bp->tstamp_config = *tstamp_config;
461 	if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)