brocade/bna/bfa_ioc_ct.c

372 	u32	r32;
377 	r32 = readl(rb + FNC_PERS_REG);
378 	r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
379 	ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
387 	u32	r32;
389 	r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);
390 	ioc->port_id = ((r32 & __FC_LL_PORT_MAP__MK) >> __FC_LL_PORT_MAP__SH);
398 	u32	r32, mode;
400 	r32 = readl(rb + FNC_PERS_REG);
402 	mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
416 	r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
417 	r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
419 	writel(r32, rb + FNC_PERS_REG);
425 	u32 r32;
427 	r32 = readl(ioc->ioc_regs.lpu_read_stat);
428 	if (r32) {
448 	u32 r32;
450 	r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
451 	if (r32 & __MSIX_VT_NUMVT__MK) {
452 		writel(r32 & __MSIX_VT_OFST_,
485 	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
486 	u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
509 	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
512 	writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
518 	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
522 	writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
528 	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
530 	writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync);
536 	u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
537 	u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
538 	u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
556 		writel(bfa_ioc_ct_clear_sync_ackd(r32),
569 		writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
603 	u32	pll_sclk, pll_fclk, r32;
661 	r32 = readl(rb + PSS_CTL_REG);
662 	r32 &= ~__PSS_LMEM_RESET;
663 	writel(r32, (rb + PSS_CTL_REG));
672 	r32 = readl(rb + MBIST_STAT_REG);
680 	u32 r32;
685 	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
686 	r32 &= ~(__APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN);
687 	r32 |= (__APP_PLL_SCLK_ENARST | __APP_PLL_SCLK_BYPASS |
689 	writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
695 	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
696 	r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
697 	writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
702 	r32 = readl(rb + CT2_CHIP_MISC_PRG);
703 	writel(r32 | __ETH_CLK_ENABLE_PORT0,
706 	r32 = readl(rb + CT2_PCIE_MISC_REG);
707 	writel(r32 | __ETH_CLK_ENABLE_PORT1,
713 	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
714 	r32 &= (__P_SCLK_PLL_LOCK | __APP_PLL_SCLK_REFCLK_SEL |
716 	writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG);
732 	u32 r32;
737 	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
738 	r32 &= ~(__APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN);
739 	r32 |= (__APP_PLL_LCLK_ENARST | __APP_PLL_LCLK_BYPASS |
741 	writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
746 	r32 = readl(rb + CT2_CHIP_MISC_PRG);
747 	writel(r32, (rb + CT2_CHIP_MISC_PRG));
752 	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
753 	writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
758 	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
759 	r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
760 	r32 |= 0x20c1731b;
761 	writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
772 	u32 r32;
774 	r32 = readl(rb + PSS_CTL_REG);
775 	r32 &= ~__PSS_LMEM_RESET;
776 	writel(r32, rb + PSS_CTL_REG);
787 	volatile u32 r32;
795 	r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
796 	writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
802 	r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
803 	writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
820 	volatile u32 r32;
822 	r32 = readl(rb + CT2_NFC_CSR_SET_REG);
823 	if (r32 & __NFC_CONTROLLER_HALTED)
832 	volatile u32 r32;
837 		r32 = readl(rb + CT2_NFC_CSR_SET_REG);
838 		if (!(r32 & __NFC_CONTROLLER_HALTED))
848 	volatile u32 wgn, r32;
863 			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
864 			if (r32 & __RESET_AND_START_SCLK_LCLK_PLLS)
867 		BUG_ON(!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS));
870 			r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
871 			if (!(r32 & __RESET_AND_START_SCLK_LCLK_PLLS))
874 		BUG_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);
877 		r32 = readl(rb + CT2_CSI_FW_CTL_REG);
878 		BUG_ON(r32 & __RESET_AND_START_SCLK_LCLK_PLLS);
882 			r32 = readl(rb + CT2_NFC_CSR_SET_REG);
883 			if (r32 & __NFC_CONTROLLER_HALTED)
893 		r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG);
894 		writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
896 		r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG);
897 		writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
903 		r32 = readl(rb + PSS_GPIO_OUT_REG);
904 		writel(r32 & ~1, rb + PSS_GPIO_OUT_REG);
905 		r32 = readl(rb + PSS_GPIO_OE_REG);
906 		writel(r32 | 1, rb + PSS_GPIO_OE_REG);
917 	r32 = readl(rb + HOST_SEM5_REG);
918 	if (r32 & 0x1) {
919 		r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT);
920 		if (r32 == 1) {
924 		r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT);
925 		if (r32 == 1) {