Lines Matching refs:bp
36 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
37 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
38 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
41 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
46 for_each_rx_queue_cnic(bp, i) {
47 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), bnx2x_poll);
51 static void bnx2x_add_all_napi(struct bnx2x *bp)
56 for_each_eth_queue(bp, i) {
57 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), bnx2x_poll);
61 static int bnx2x_calc_num_queues(struct bnx2x *bp)
69 nq = clamp(nq, 1, BNX2X_MAX_QUEUES(bp));
76 * @bp: driver handle
80 * Makes sure the contents of the bp->fp[to].napi is kept
86 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
88 struct bnx2x_fastpath *from_fp = &bp->fp[from];
89 struct bnx2x_fastpath *to_fp = &bp->fp[to];
90 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
91 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
92 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
93 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
121 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
122 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
123 (bp)->max_cos;
124 if (from == FCOE_IDX(bp)) {
129 memcpy(&bp->bnx2x_txq[new_txdata_index],
130 &bp->bnx2x_txq[old_txdata_index],
132 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
138 * @bp: driver handle
143 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
145 if (IS_PF(bp)) {
149 bnx2x_get_ext_phy_fw_version(&bp->link_params,
154 bp->fw_ver,
155 (bp->common.bc_ver & 0xff0000) >> 16,
156 (bp->common.bc_ver & 0xff00) >> 8,
157 (bp->common.bc_ver & 0xff),
160 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
167 * @bp: driver handle
170 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
172 int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
177 for (cos = 1; cos < bp->max_cos; cos++) {
179 struct bnx2x_fastpath *fp = &bp->fp[i];
182 memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
184 fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
194 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
245 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
253 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
273 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
280 if (unlikely(bp->panic))
284 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
300 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
336 (bp->state == BNX2X_STATE_OPEN) &&
337 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
358 struct bnx2x *bp = fp->bp;
410 static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
415 if ((bp->dev->features & NETIF_F_RXHASH) &&
434 struct bnx2x *bp = fp->bp;
447 mapping = dma_map_single(&bp->pdev->dev,
456 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
480 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
547 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
563 mapping = dma_map_page(&bp->pdev->dev, pool->page,
565 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
586 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
638 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, GFP_ATOMIC);
640 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
644 dma_unmap_page(&bp->pdev->dev,
710 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
722 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
734 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
738 gro_func(bp, skb);
743 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
750 bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
753 bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
756 netdev_WARN_ONCE(bp->dev,
766 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
792 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
812 skb->protocol = eth_type_trans(skb, bp->dev);
815 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
819 bnx2x_gro_receive(bp, fp, skb);
837 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
840 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
852 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
855 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
896 struct bnx2x *bp = fp->bp;
904 if (unlikely(bp->panic))
934 if (unlikely(bp->panic))
1013 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
1016 if (bp->panic)
1026 dma_sync_single_for_cpu(&bp->pdev->dev,
1037 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
1044 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1050 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1056 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1058 dma_unmap_single(&bp->pdev->dev,
1065 bnx2x_fp_qstats(bp, fp)->
1073 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1081 skb->protocol = eth_type_trans(skb, bp->dev);
1084 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1089 if (bp->dev->features & NETIF_F_RXCSUM)
1091 bnx2x_fp_qstats(bp, fp));
1098 bnx2x_set_rx_ts(bp, skb);
1134 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1143 struct bnx2x *bp = fp->bp;
1150 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1153 if (unlikely(bp->panic))
1162 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1168 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1170 mutex_lock(&bp->port.phy_mutex);
1172 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1175 void bnx2x_release_phy_lock(struct bnx2x *bp)
1177 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1179 mutex_unlock(&bp->port.phy_mutex);
1183 u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1185 u16 line_speed = bp->link_vars.line_speed;
1186 if (IS_MF(bp)) {
1187 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1188 bp->mf_config[BP_VN(bp)]);
1193 if (IS_MF_PERCENT_BW(bp))
1209 * @bp: driver handle
1214 static void bnx2x_fill_report_data(struct bnx2x *bp,
1219 if (IS_PF(bp)) {
1221 data->line_speed = bnx2x_get_mf_speed(bp);
1224 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1228 if (!BNX2X_NUM_ETH_QUEUES(bp))
1233 if (bp->link_vars.duplex == DUPLEX_FULL)
1238 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1243 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1247 *data = bp->vf_link_vars;
1254 * @bp: driver handle
1261 void bnx2x_link_report(struct bnx2x *bp)
1263 bnx2x_acquire_phy_lock(bp);
1264 __bnx2x_link_report(bp);
1265 bnx2x_release_phy_lock(bp);
1271 * @bp: driver handle
1276 void __bnx2x_link_report(struct bnx2x *bp)
1280 if (bp->force_link_down) {
1281 bp->link_vars.link_up = 0;
1286 if (IS_PF(bp) && !CHIP_IS_E1(bp))
1287 bnx2x_read_mf_cfg(bp);
1290 bnx2x_fill_report_data(bp, &cur_data);
1293 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1295 &bp->last_reported_link.link_report_flags) &&
1300 bp->link_cnt++;
1305 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1308 if (IS_PF(bp))
1309 bnx2x_iov_link_update(bp);
1313 netif_carrier_off(bp->dev);
1314 netdev_err(bp->dev, "NIC Link is Down\n");
1320 netif_carrier_on(bp->dev);
1346 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1369 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1384 dma_unmap_single(&bp->pdev->dev,
1392 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1396 for_each_rx_queue_cnic(bp, j) {
1397 struct bnx2x_fastpath *fp = &bp->fp[j];
1406 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1411 void bnx2x_init_rx_rings(struct bnx2x *bp)
1413 int func = BP_FUNC(bp);
1418 for_each_eth_queue(bp, j) {
1419 struct bnx2x_fastpath *fp = &bp->fp[j];
1422 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1426 for (i = 0; i < MAX_AGG_QS(bp); i++) {
1437 bnx2x_free_tpa_pool(bp, fp, i);
1455 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1462 bnx2x_free_rx_sge_range(bp, fp,
1464 bnx2x_free_tpa_pool(bp, fp,
1465 MAX_AGG_QS(bp));
1477 for_each_eth_queue(bp, j) {
1478 struct bnx2x_fastpath *fp = &bp->fp[j];
1487 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1493 if (CHIP_IS_E1(bp)) {
1494 REG_WR(bp, BAR_USTRORM_INTMEM +
1497 REG_WR(bp, BAR_USTRORM_INTMEM +
1507 struct bnx2x *bp = fp->bp;
1517 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1523 netdev_get_tx_queue(bp->dev,
1528 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1532 for_each_tx_queue_cnic(bp, i) {
1533 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1537 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1541 for_each_eth_queue(bp, i) {
1542 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1548 struct bnx2x *bp = fp->bp;
1561 dma_unmap_single(&bp->pdev->dev,
1570 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1574 for_each_rx_queue_cnic(bp, j) {
1575 bnx2x_free_rx_bds(&bp->fp[j]);
1579 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1583 for_each_eth_queue(bp, j) {
1584 struct bnx2x_fastpath *fp = &bp->fp[j];
1589 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1593 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1595 bnx2x_free_tx_skbs_cnic(bp);
1596 bnx2x_free_rx_skbs_cnic(bp);
1599 void bnx2x_free_skbs(struct bnx2x *bp)
1601 bnx2x_free_tx_skbs(bp);
1602 bnx2x_free_rx_skbs(bp);
1605 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1608 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1610 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1618 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1625 * @bp: driver handle
1628 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1636 if (IS_PF(bp)) {
1637 free_irq(bp->msix_table[offset].vector, bp->dev);
1639 bp->msix_table[offset].vector);
1643 if (CNIC_SUPPORT(bp)) {
1649 for_each_eth_queue(bp, i) {
1653 i, bp->msix_table[offset].vector);
1655 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1659 void bnx2x_free_irq(struct bnx2x *bp)
1661 if (bp->flags & USING_MSIX_FLAG &&
1662 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1663 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1666 if (IS_PF(bp))
1669 bnx2x_free_msix_irqs(bp, nvecs);
1671 free_irq(bp->dev->irq, bp->dev);
1675 int bnx2x_enable_msix(struct bnx2x *bp)
1680 if (IS_PF(bp)) {
1681 bp->msix_table[msix_vec].entry = msix_vec;
1683 bp->msix_table[0].entry);
1688 if (CNIC_SUPPORT(bp)) {
1689 bp->msix_table[msix_vec].entry = msix_vec;
1691 msix_vec, bp->msix_table[msix_vec].entry);
1696 for_each_eth_queue(bp, i) {
1697 bp->msix_table[msix_vec].entry = msix_vec;
1706 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1707 BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1714 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1722 bp->flags |= USING_SINGLE_MSIX_FLAG;
1725 bp->num_ethernet_queues = 1;
1726 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1739 bp->num_ethernet_queues -= diff;
1740 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1743 bp->num_queues);
1746 bp->flags |= USING_MSIX_FLAG;
1753 bp->flags |= DISABLE_MSI_FLAG;
1758 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1763 if (IS_PF(bp)) {
1764 rc = request_irq(bp->msix_table[offset++].vector,
1766 bp->dev->name, bp->dev);
1773 if (CNIC_SUPPORT(bp))
1776 for_each_eth_queue(bp, i) {
1777 struct bnx2x_fastpath *fp = &bp->fp[i];
1779 bp->dev->name, i);
1781 rc = request_irq(bp->msix_table[offset].vector,
1785 bp->msix_table[offset].vector, rc);
1786 bnx2x_free_msix_irqs(bp, offset);
1793 i = BNX2X_NUM_ETH_QUEUES(bp);
1794 if (IS_PF(bp)) {
1795 offset = 1 + CNIC_SUPPORT(bp);
1796 netdev_info(bp->dev,
1798 bp->msix_table[0].vector,
1799 0, bp->msix_table[offset].vector,
1800 i - 1, bp->msix_table[offset + i - 1].vector);
1802 offset = CNIC_SUPPORT(bp);
1803 netdev_info(bp->dev,
1805 0, bp->msix_table[offset].vector,
1806 i - 1, bp->msix_table[offset + i - 1].vector);
1811 int bnx2x_enable_msi(struct bnx2x *bp)
1815 rc = pci_enable_msi(bp->pdev);
1820 bp->flags |= USING_MSI_FLAG;
1825 static int bnx2x_req_irq(struct bnx2x *bp)
1830 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1835 if (bp->flags & USING_MSIX_FLAG)
1836 irq = bp->msix_table[0].vector;
1838 irq = bp->pdev->irq;
1840 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1843 static int bnx2x_setup_irqs(struct bnx2x *bp)
1846 if (bp->flags & USING_MSIX_FLAG &&
1847 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1848 rc = bnx2x_req_msix_irqs(bp);
1852 rc = bnx2x_req_irq(bp);
1857 if (bp->flags & USING_MSI_FLAG) {
1858 bp->dev->irq = bp->pdev->irq;
1859 netdev_info(bp->dev, "using MSI IRQ %d\n",
1860 bp->dev->irq);
1862 if (bp->flags & USING_MSIX_FLAG) {
1863 bp->dev->irq = bp->msix_table[0].vector;
1864 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1865 bp->dev->irq);
1872 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1876 for_each_rx_queue_cnic(bp, i) {
1877 napi_enable(&bnx2x_fp(bp, i, napi));
1881 static void bnx2x_napi_enable(struct bnx2x *bp)
1885 for_each_eth_queue(bp, i) {
1886 napi_enable(&bnx2x_fp(bp, i, napi));
1890 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1894 for_each_rx_queue_cnic(bp, i) {
1895 napi_disable(&bnx2x_fp(bp, i, napi));
1899 static void bnx2x_napi_disable(struct bnx2x *bp)
1903 for_each_eth_queue(bp, i) {
1904 napi_disable(&bnx2x_fp(bp, i, napi));
1908 void bnx2x_netif_start(struct bnx2x *bp)
1910 if (netif_running(bp->dev)) {
1911 bnx2x_napi_enable(bp);
1912 if (CNIC_LOADED(bp))
1913 bnx2x_napi_enable_cnic(bp);
1914 bnx2x_int_enable(bp);
1915 if (bp->state == BNX2X_STATE_OPEN)
1916 netif_tx_wake_all_queues(bp->dev);
1920 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1922 bnx2x_int_disable_sync(bp, disable_hw);
1923 bnx2x_napi_disable(bp);
1924 if (CNIC_LOADED(bp))
1925 bnx2x_napi_disable_cnic(bp);
1931 struct bnx2x *bp = netdev_priv(dev);
1933 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1946 return bnx2x_fcoe_tx(bp, txq_index);
1951 (BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos);
1954 void bnx2x_set_num_queues(struct bnx2x *bp)
1957 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1960 if (IS_MF_STORAGE_ONLY(bp))
1961 bp->num_ethernet_queues = 1;
1964 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1965 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1967 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1973 * @bp: Driver handle
1978 * bp->max_cos.
1993 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1997 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1998 rx = BNX2X_NUM_ETH_QUEUES(bp);
2001 if (include_cnic && !NO_FCOE(bp)) {
2006 rc = netif_set_real_num_tx_queues(bp->dev, tx);
2011 rc = netif_set_real_num_rx_queues(bp->dev, rx);
2023 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
2027 for_each_queue(bp, i) {
2028 struct bnx2x_fastpath *fp = &bp->fp[i];
2041 mtu = bp->dev->mtu;
2056 static int bnx2x_init_rss(struct bnx2x *bp)
2059 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2064 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2065 bp->rss_conf_obj.ind_table[i] =
2066 bp->fp->cl_id +
2077 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2080 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2088 * if (!is_eth_multi(bp))
2089 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
2109 if (!CHIP_IS_E1x(bp)) {
2132 if (IS_PF(bp))
2133 return bnx2x_config_rss(bp, ¶ms);
2135 return bnx2x_vfpf_config_rss(bp, ¶ms);
2138 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
2145 func_params.f_obj = &bp->func_obj;
2150 return bnx2x_func_state_change(bp, &func_params);
2157 void bnx2x_squeeze_objects(struct bnx2x *bp)
2162 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2173 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2181 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2187 rparam.mcast_obj = &bp->mcast_obj;
2194 netif_addr_lock_bh(bp->dev);
2195 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2201 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2206 netif_addr_unlock_bh(bp->dev);
2210 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2212 netif_addr_unlock_bh(bp->dev);
2216 #define LOAD_ERROR_EXIT(bp, label) \
2218 (bp)->state = BNX2X_STATE_ERROR; \
2222 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2224 bp->cnic_loaded = false; \
2228 #define LOAD_ERROR_EXIT(bp, label) \
2230 (bp)->state = BNX2X_STATE_ERROR; \
2231 (bp)->panic = 1; \
2234 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2236 bp->cnic_loaded = false; \
2237 (bp)->panic = 1; \
2242 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2244 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2245 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2249 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2252 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2255 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2262 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2265 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2269 if (IS_SRIOV(bp))
2270 vf_headroom = bnx2x_vf_headroom(bp);
2278 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2279 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2283 bp->fw_stats_num, vf_headroom, num_groups);
2284 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2295 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2301 bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2302 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2303 if (!bp->fw_stats)
2307 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2308 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2309 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2310 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2311 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2312 bp->fw_stats_req_sz;
2315 U64_HI(bp->fw_stats_req_mapping),
2316 U64_LO(bp->fw_stats_req_mapping));
2318 U64_HI(bp->fw_stats_data_mapping),
2319 U64_LO(bp->fw_stats_data_mapping));
2323 bnx2x_free_fw_stats_mem(bp);
2329 static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2334 bp->fw_seq =
2335 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2337 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2340 bp->fw_drv_pulse_wr_seq =
2341 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2343 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2347 if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2351 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2373 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err)
2382 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2409 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2411 int path = BP_PATH(bp);
2430 static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2435 bp->port.pmf = 1;
2437 * writing to bp->port.pmf here and reading it from the
2442 bp->port.pmf = 0;
2445 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2448 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2452 (bp->common.shmem2_base)) {
2453 if (SHMEM2_HAS(bp, dcc_support))
2454 SHMEM2_WR(bp, dcc_support,
2457 if (SHMEM2_HAS(bp, afex_driver_support))
2458 SHMEM2_WR(bp, afex_driver_support,
2463 bp->afex_def_vlan_tag = -1;
2469 * @bp: driver handle
2472 * Makes sure the contents of the bp->fp[index].napi is kept
2475 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2477 struct bnx2x_fastpath *fp = &bp->fp[index];
2491 fp->bp = bp;
2494 fp->max_cos = bp->max_cos;
2501 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2504 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2505 BNX2X_NUM_ETH_QUEUES(bp) + index];
2510 if (bp->dev->features & NETIF_F_LRO)
2512 else if (bp->dev->features & NETIF_F_GRO_HW)
2517 /* We don't want TPA if it's disabled in bp
2520 if (bp->disable_tpa || IS_FCOE_FP(fp))
2524 void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state)
2528 if (!IS_MF_BD(bp) || !SHMEM2_HAS(bp, os_driver_state) || IS_VF(bp))
2531 cur = SHMEM2_RD(bp, os_driver_state[BP_FW_MB_IDX(bp)]);
2535 SHMEM2_WR(bp, os_driver_state[BP_FW_MB_IDX(bp)], state);
2538 int bnx2x_load_cnic(struct bnx2x *bp)
2540 int i, rc, port = BP_PORT(bp);
2544 mutex_init(&bp->cnic_mutex);
2546 if (IS_PF(bp)) {
2547 rc = bnx2x_alloc_mem_cnic(bp);
2549 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2550 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2554 rc = bnx2x_alloc_fp_mem_cnic(bp);
2557 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2561 rc = bnx2x_set_real_num_queues(bp, 1);
2564 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2568 bnx2x_add_all_napi_cnic(bp);
2570 bnx2x_napi_enable_cnic(bp);
2572 rc = bnx2x_init_hw_func_cnic(bp);
2574 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2576 bnx2x_nic_init_cnic(bp);
2578 if (IS_PF(bp)) {
2580 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2583 for_each_cnic_queue(bp, i) {
2584 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2587 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2593 bnx2x_set_rx_mode_inner(bp);
2596 bnx2x_get_iscsi_info(bp);
2597 bnx2x_setup_cnic_irq_info(bp);
2598 bnx2x_setup_cnic_info(bp);
2599 bp->cnic_loaded = true;
2600 if (bp->state == BNX2X_STATE_OPEN)
2601 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2610 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2613 bnx2x_napi_disable_cnic(bp);
2615 if (bnx2x_set_real_num_queues(bp, 0))
2619 bnx2x_free_fp_mem_cnic(bp);
2620 bnx2x_free_mem_cnic(bp);
2626 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2628 int port = BP_PORT(bp);
2633 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2636 if (unlikely(bp->panic)) {
2642 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2645 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2647 &bp->last_reported_link.link_report_flags);
2649 if (IS_PF(bp))
2651 bnx2x_ilt_set_info(bp);
2655 * allocated only once, fp index, max_cos, bp pointer.
2658 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2659 for_each_queue(bp, i)
2660 bnx2x_bz_fp(bp, i);
2661 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2662 bp->num_cnic_queues) *
2665 bp->fcoe_init = false;
2668 bnx2x_set_rx_buf_size(bp);
2670 if (IS_PF(bp)) {
2671 rc = bnx2x_alloc_mem(bp);
2673 BNX2X_ERR("Unable to allocate bp memory\n");
2681 rc = bnx2x_alloc_fp_mem(bp);
2684 LOAD_ERROR_EXIT(bp, load_error0);
2688 rc = bnx2x_alloc_fw_stats_mem(bp);
2690 LOAD_ERROR_EXIT(bp, load_error0);
2693 if (IS_VF(bp)) {
2694 rc = bnx2x_vfpf_init(bp);
2696 LOAD_ERROR_EXIT(bp, load_error0);
2700 * bp->num_queues, bnx2x_set_real_num_queues() should always
2703 rc = bnx2x_set_real_num_queues(bp, 0);
2706 LOAD_ERROR_EXIT(bp, load_error0);
2713 bnx2x_setup_tc(bp->dev, bp->max_cos);
2716 bnx2x_add_all_napi(bp);
2718 bnx2x_napi_enable(bp);
2719 bp->nic_stopped = false;
2721 if (IS_PF(bp)) {
2723 bnx2x_set_pf_load(bp);
2726 if (!BP_NOMCP(bp)) {
2728 rc = bnx2x_nic_load_request(bp, &load_code);
2730 LOAD_ERROR_EXIT(bp, load_error1);
2733 rc = bnx2x_compare_fw_ver(bp, load_code, true);
2735 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2736 LOAD_ERROR_EXIT(bp, load_error2);
2739 load_code = bnx2x_nic_load_no_mcp(bp, port);
2743 bnx2x_nic_load_pmf(bp, load_code);
2746 bnx2x__init_func_obj(bp);
2749 rc = bnx2x_init_hw(bp, load_code);
2752 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2753 LOAD_ERROR_EXIT(bp, load_error2);
2757 bnx2x_pre_irq_nic_init(bp);
2760 rc = bnx2x_setup_irqs(bp);
2763 if (IS_PF(bp))
2764 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2765 LOAD_ERROR_EXIT(bp, load_error2);
2769 if (IS_PF(bp)) {
2771 bnx2x_post_irq_nic_init(bp, load_code);
2773 bnx2x_init_bp_objs(bp);
2774 bnx2x_iov_nic_init(bp);
2777 bp->afex_def_vlan_tag = -1;
2778 bnx2x_nic_load_afex_dcc(bp, load_code);
2779 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2780 rc = bnx2x_func_start(bp);
2783 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2785 LOAD_ERROR_EXIT(bp, load_error3);
2789 if (!BP_NOMCP(bp)) {
2790 load_code = bnx2x_fw_command(bp,
2795 LOAD_ERROR_EXIT(bp, load_error3);
2800 bnx2x_update_coalesce(bp);
2804 rc = bnx2x_setup_leading(bp);
2807 LOAD_ERROR_EXIT(bp, load_error3);
2811 for_each_nondefault_eth_queue(bp, i) {
2812 if (IS_PF(bp))
2813 rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2815 rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2818 LOAD_ERROR_EXIT(bp, load_error3);
2823 rc = bnx2x_init_rss(bp);
2826 LOAD_ERROR_EXIT(bp, load_error3);
2830 bp->state = BNX2X_STATE_OPEN;
2833 if (IS_PF(bp))
2834 rc = bnx2x_set_eth_mac(bp, true);
2836 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2840 LOAD_ERROR_EXIT(bp, load_error3);
2843 if (IS_PF(bp) && bp->pending_max) {
2844 bnx2x_update_max_mf_config(bp, bp->pending_max);
2845 bp->pending_max = 0;
2848 bp->force_link_down = false;
2849 if (bp->port.pmf) {
2850 rc = bnx2x_initial_phy_init(bp, load_mode);
2852 LOAD_ERROR_EXIT(bp, load_error3);
2854 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2859 rc = bnx2x_vlan_reconfigure_vid(bp);
2861 LOAD_ERROR_EXIT(bp, load_error3);
2864 bnx2x_set_rx_mode_inner(bp);
2866 if (bp->flags & PTP_SUPPORTED) {
2867 bnx2x_register_phc(bp);
2868 bnx2x_init_ptp(bp);
2869 bnx2x_configure_ptp_filters(bp);
2875 netif_tx_wake_all_queues(bp->dev);
2879 netif_tx_start_all_queues(bp->dev);
2885 bp->state = BNX2X_STATE_DIAG;
2892 if (bp->port.pmf)
2893 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2895 bnx2x__link_status_update(bp);
2898 mod_timer(&bp->timer, jiffies + bp->current_interval);
2900 if (CNIC_ENABLED(bp))
2901 bnx2x_load_cnic(bp);
2903 if (IS_PF(bp))
2904 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2906 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2909 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2911 val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT);
2912 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2918 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2920 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2925 if (IS_PF(bp))
2926 bnx2x_update_mfw_dump(bp);
2929 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2930 bnx2x_dcbx_init(bp, false);
2932 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
2933 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_ACTIVE);
2941 if (IS_PF(bp)) {
2942 bnx2x_int_disable_sync(bp, 1);
2945 bnx2x_squeeze_objects(bp);
2949 bnx2x_free_skbs(bp);
2950 for_each_rx_queue(bp, i)
2951 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2954 bnx2x_free_irq(bp);
2956 if (IS_PF(bp) && !BP_NOMCP(bp)) {
2957 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2958 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2961 bp->port.pmf = 0;
2963 bnx2x_napi_disable(bp);
2964 bnx2x_del_all_napi(bp);
2965 bp->nic_stopped = true;
2968 if (IS_PF(bp))
2969 bnx2x_clear_pf_load(bp);
2971 bnx2x_free_fw_stats_mem(bp);
2972 bnx2x_free_fp_mem(bp);
2973 bnx2x_free_mem(bp);
2979 int bnx2x_drain_tx_queues(struct bnx2x *bp)
2984 for_each_tx_queue(bp, i) {
2985 struct bnx2x_fastpath *fp = &bp->fp[i];
2988 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2996 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
3003 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
3004 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
3007 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
3009 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
3010 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
3014 if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
3015 (bp->state == BNX2X_STATE_CLOSED ||
3016 bp->state == BNX2X_STATE_ERROR)) {
3024 bp->recovery_state = BNX2X_RECOVERY_DONE;
3025 bp->is_leader = 0;
3026 bnx2x_release_leader_lock(bp);
3040 if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
3043 /* It's important to set the bp->state to the value different from
3047 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
3051 bnx2x_iov_channel_down(bp);
3053 if (CNIC_LOADED(bp))
3054 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
3057 bnx2x_tx_disable(bp);
3058 netdev_reset_tc(bp->dev);
3060 bp->rx_mode = BNX2X_RX_MODE_NONE;
3062 del_timer_sync(&bp->timer);
3064 if (IS_PF(bp) && !BP_NOMCP(bp)) {
3066 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
3067 bnx2x_drv_pulse(bp);
3068 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
3069 bnx2x_save_statistics(bp);
3077 bnx2x_drain_tx_queues(bp);
3082 if (IS_VF(bp)) {
3083 bnx2x_clear_vlan_info(bp);
3084 bnx2x_vfpf_close_vf(bp);
3087 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3090 bnx2x_send_unload_req(bp, unload_mode);
3098 if (!CHIP_IS_E1x(bp))
3099 bnx2x_pf_disable(bp);
3101 if (!bp->nic_stopped) {
3103 bnx2x_netif_stop(bp, 1);
3105 bnx2x_del_all_napi(bp);
3106 if (CNIC_LOADED(bp))
3107 bnx2x_del_all_napi_cnic(bp);
3109 bnx2x_free_irq(bp);
3110 bp->nic_stopped = true;
3114 bnx2x_send_unload_done(bp, false);
3121 if (IS_PF(bp))
3122 bnx2x_squeeze_objects(bp);
3125 bp->sp_state = 0;
3127 bp->port.pmf = 0;
3130 bp->sp_rtnl_state = 0;
3134 bnx2x_free_skbs(bp);
3135 if (CNIC_LOADED(bp))
3136 bnx2x_free_skbs_cnic(bp);
3137 for_each_rx_queue(bp, i)
3138 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3140 bnx2x_free_fp_mem(bp);
3141 if (CNIC_LOADED(bp))
3142 bnx2x_free_fp_mem_cnic(bp);
3144 if (IS_PF(bp)) {
3145 if (CNIC_LOADED(bp))
3146 bnx2x_free_mem_cnic(bp);
3148 bnx2x_free_mem(bp);
3150 bp->state = BNX2X_STATE_CLOSED;
3151 bp->cnic_loaded = false;
3154 if (IS_PF(bp) && !BP_NOMCP(bp))
3155 bnx2x_update_mng_version(bp);
3160 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3161 bnx2x_set_reset_in_progress(bp);
3165 bnx2x_set_reset_global(bp);
3171 if (IS_PF(bp) &&
3172 !bnx2x_clear_pf_load(bp) &&
3173 bnx2x_reset_is_done(bp, BP_PATH(bp)))
3174 bnx2x_disable_close_the_gate(bp);
3181 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
3186 if (!bp->pdev->pm_cap) {
3191 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
3195 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3207 if (atomic_read(&bp->pdev->enable_cnt) != 1)
3210 if (CHIP_REV_IS_SLOW(bp))
3216 if (bp->wol)
3219 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3228 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
3241 struct bnx2x *bp = fp->bp;
3246 if (unlikely(bp->panic)) {
3253 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
3286 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3303 static u16 bnx2x_tx_split(struct bnx2x *bp,
3362 static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
3380 if (!CHIP_IS_E1x(bp) && skb->encapsulation) {
3419 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3530 * @bp: driver handle
3537 static u8 bnx2x_set_pbd_csum_enc(struct bnx2x *bp, struct sk_buff *skb,
3562 * @bp: driver handle
3569 static u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3591 static void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3607 * @bp: driver handle
3612 static u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3753 struct bnx2x *bp = netdev_priv(dev);
3767 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3775 if (unlikely(bp->panic))
3782 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
3784 txdata = &bp->bnx2x_txq[txq_index];
3795 if (unlikely(bnx2x_tx_avail(bp, txdata) <
3802 bnx2x_fp_qstats(bp, txdata->parent_fp);
3807 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3834 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3836 bp->lin_cnt++;
3846 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3848 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3880 if (!(bp->flags & TX_TIMESTAMPING_EN)) {
3881 bp->eth_stats.ptp_skip_tx_ts++;
3883 } else if (bp->ptp_tx_skb) {
3884 bp->eth_stats.ptp_skip_tx_ts++;
3885 netdev_err_once(bp->dev,
3890 bp->ptp_tx_skb = skb_get(skb);
3891 bp->ptp_tx_start = jiffies;
3892 schedule_work(&bp->ptp_task);
3919 if (IS_VF(bp)) {
3946 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
3948 if (!CHIP_IS_E1x(bp)) {
3956 hlen = bnx2x_set_pbd_csum_enc(bp, skb,
3990 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3999 if (IS_VF(bp)) {
4011 if (bp->flags & TX_SWITCHING)
4036 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
4067 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
4071 if (!CHIP_IS_E1x(bp))
4092 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
4094 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
4106 bnx2x_free_tx_pkt(bp, txdata,
4190 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
4194 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
4202 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
4203 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
4211 void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default)
4213 int mfw_vn = BP_FW_MB_IDX(bp);
4217 if (!IS_MF_BD(bp)) {
4227 tmp = SHMEM2_RD(bp, c2s_pcp_map_lower[mfw_vn]);
4234 tmp = SHMEM2_RD(bp, c2s_pcp_map_upper[mfw_vn]);
4241 tmp = SHMEM2_RD(bp, c2s_pcp_map_default[mfw_vn]);
4256 struct bnx2x *bp = netdev_priv(dev);
4270 if (num_tc > bp->max_cos) {
4272 num_tc, bp->max_cos);
4282 bnx2x_get_c2s_mapping(bp, c2s_map, &c2s_def);
4288 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[outer_prio]);
4291 outer_prio, bp->prio_to_cos[outer_prio]);
4305 for (cos = 0; cos < bp->max_cos; cos++) {
4306 count = BNX2X_NUM_ETH_QUEUES(bp);
4307 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
4334 struct bnx2x *bp = netdev_priv(dev);
4342 if (IS_MF_STORAGE_ONLY(bp)) {
4348 rc = bnx2x_set_eth_mac(bp, false);
4356 rc = bnx2x_set_eth_mac(bp, true);
4358 if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
4359 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
4364 static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
4366 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
4367 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
4377 if (!CHIP_IS_E1x(bp))
4379 bnx2x_fp(bp, fp_index,
4384 bnx2x_fp(bp, fp_index,
4390 if (!skip_rx_queue(bp, fp_index)) {
4394 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
4395 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
4396 bnx2x_fp(bp, fp_index, rx_desc_mapping),
4399 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
4400 bnx2x_fp(bp, fp_index, rx_comp_mapping),
4405 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
4406 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
4407 bnx2x_fp(bp, fp_index, rx_sge_mapping),
4412 if (!skip_tx_queue(bp, fp_index)) {
4430 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
4433 for_each_cnic_queue(bp, i)
4434 bnx2x_free_fp_mem_at(bp, i);
4437 void bnx2x_free_fp_mem(struct bnx2x *bp)
4440 for_each_eth_queue(bp, i)
4441 bnx2x_free_fp_mem_at(bp, i);
4444 static void set_sb_shortcuts(struct bnx2x *bp, int index)
4446 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
4447 if (!CHIP_IS_E1x(bp)) {
4448 bnx2x_fp(bp, index, sb_index_values) =
4450 bnx2x_fp(bp, index, sb_running_index) =
4453 bnx2x_fp(bp, index, sb_index_values) =
4455 bnx2x_fp(bp, index, sb_running_index) =
4464 struct bnx2x *bp = fp->bp;
4475 if (bnx2x_alloc_rx_data(bp, fp, ring_prod, GFP_KERNEL) < 0) {
4493 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
4516 static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
4519 struct bnx2x_fastpath *fp = &bp->fp[index];
4524 if (!bp->rx_ring_size && IS_MF_STORAGE_ONLY(bp)) {
4526 bp->rx_ring_size = rx_ring_size;
4527 } else if (!bp->rx_ring_size) {
4528 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
4530 if (CHIP_IS_E3(bp)) {
4531 u32 cfg = SHMEM_RD(bp,
4532 dev_info.port_hw_config[BP_PORT(bp)].
4542 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4545 bp->rx_ring_size = rx_ring_size;
4547 rx_ring_size = bp->rx_ring_size;
4552 sb = &bnx2x_fp(bp, index, status_blk);
4556 if (!CHIP_IS_E1x(bp)) {
4557 sb->e2_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4562 sb->e1x_sb = BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, status_blk_mapping),
4573 set_sb_shortcuts(bp, index);
4576 if (!skip_tx_queue(bp, index)) {
4598 if (!skip_rx_queue(bp, index)) {
4600 bnx2x_fp(bp, index, rx_buf_ring) =
4602 if (!bnx2x_fp(bp, index, rx_buf_ring))
4604 bnx2x_fp(bp, index, rx_desc_ring) =
4605 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_desc_mapping),
4607 if (!bnx2x_fp(bp, index, rx_desc_ring))
4611 bnx2x_fp(bp, index, rx_comp_ring) =
4612 BNX2X_PCI_FALLOC(&bnx2x_fp(bp, index, rx_comp_mapping),
4614 if (!bnx2x_fp(bp, index, rx_comp_ring))
4618 bnx2x_fp(bp, index, rx_page_ring) =
4621 if (!bnx2x_fp(bp, index, rx_page_ring))
4623 bnx2x_fp(bp, index, rx_sge_ring) =
4624 BNX2X_PCI_ALLOC(&bnx2x_fp(bp, index, rx_sge_mapping),
4626 if (!bnx2x_fp(bp, index, rx_sge_ring))
4653 bnx2x_free_fp_mem_at(bp, index);
4659 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
4661 if (!NO_FCOE(bp))
4663 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4672 static int bnx2x_alloc_fp_mem(struct bnx2x *bp)
4681 if (bnx2x_alloc_fp_mem_at(bp, 0))
4685 for_each_nondefault_eth_queue(bp, i)
4686 if (bnx2x_alloc_fp_mem_at(bp, i))
4690 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4691 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4694 bnx2x_shrink_eth_fp(bp, delta);
4695 if (CNIC_SUPPORT(bp))
4702 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4703 bp->num_ethernet_queues -= delta;
4704 bp->num_queues = bp->num_ethernet_queues +
4705 bp->num_cnic_queues;
4707 bp->num_queues + delta, bp->num_queues);
4713 void bnx2x_free_mem_bp(struct bnx2x *bp)
4717 for (i = 0; i < bp->fp_array_size; i++)
4718 kfree(bp->fp[i].tpa_info);
4719 kfree(bp->fp);
4720 kfree(bp->sp_objs);
4721 kfree(bp->fp_stats);
4722 kfree(bp->bnx2x_txq);
4723 kfree(bp->msix_table);
4724 kfree(bp->ilt);
4727 int bnx2x_alloc_mem_bp(struct bnx2x *bp)
4740 msix_table_size = bp->igu_sb_cnt;
4741 if (IS_PF(bp))
4746 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
4747 bp->fp_array_size = fp_array_size;
4748 BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size);
4750 fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL);
4753 for (i = 0; i < bp->fp_array_size; i++) {
4761 bp->fp = fp;
4764 bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs),
4766 if (!bp->sp_objs)
4770 bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats),
4772 if (!bp->fp_stats)
4777 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4780 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4782 if (!bp->bnx2x_txq)
4789 bp->msix_table = tbl;
4795 bp->ilt = ilt;
4799 bnx2x_free_mem_bp(bp);
4805 struct bnx2x *bp = netdev_priv(dev);
4810 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
4811 return bnx2x_nic_load(bp, LOAD_NORMAL);
4814 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4817 if (bp->link_params.num_phys <= 1)
4820 if (bp->link_vars.link_up) {
4823 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4824 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4828 switch (bnx2x_phy_selection(&bp->link_params)) {
4843 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4845 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4852 if (bp->link_params.multi_phy_config &
4865 struct bnx2x *bp = netdev_priv(dev);
4866 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4889 struct bnx2x *bp = netdev_priv(dev);
4891 if (pci_num_vf(bp->pdev)) {
4896 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4910 if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
4911 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
4919 struct bnx2x *bp = netdev_priv(dev);
4921 if (pci_num_vf(bp->pdev)) {
4927 if (!(features & NETIF_F_RXCSUM) && !bp->disable_tpa) {
4952 struct bnx2x *bp = netdev_priv(dev);
4958 if (!pci_num_vf(bp->pdev)) {
4960 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4961 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4965 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4966 bp->link_params.loopback_mode = LOOPBACK_NONE;
4979 if (bp->recovery_state == BNX2X_RECOVERY_DONE) {
4992 struct bnx2x *bp = netdev_priv(dev);
4997 if (!bp->panic)
4999 bnx2x_panic_dump(bp, false);
5005 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_TX_TIMEOUT, 0);
5012 struct bnx2x *bp;
5018 bp = netdev_priv(dev);
5029 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
5040 struct bnx2x *bp;
5047 bp = netdev_priv(dev);
5049 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
5063 rc = bnx2x_nic_load(bp, LOAD_OPEN);
5072 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
5082 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
5086 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
5090 static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
5096 REG_WR8(bp, addr, ticks);
5102 static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
5109 u8 flags = REG_RD8(bp, addr);
5113 REG_WR8(bp, addr, flags);
5119 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
5122 int port = BP_PORT(bp);
5125 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
5128 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
5131 void bnx2x_schedule_sp_rtnl(struct bnx2x *bp, enum sp_rtnl_flag flag,
5135 set_bit(flag, &bp->sp_rtnl_state);
5139 schedule_delayed_work(&bp->sp_rtnl_task, 0);