atheros/atlx/atl1.c

340 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
358 		*phy_data = (u16) val;
587 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
592 	val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
638 	u16 phy_data;
642 		phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
646 			phy_data =
651 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
654 			phy_data =
659 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
664 	ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
870 	u16 phy_data;
873 	ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
877 	if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
880 	switch (phy_data & MII_ATLX_PSSR_SPEED) {
895 	if (phy_data & MII_ATLX_PSSR_DPLX)
1283 	u16 speed, duplex, phy_data;
1287 	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1288 	atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1289 	if (!(phy_data & BMSR_LSTATUS)) {
1361 			phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1365 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1368 			phy_data =
1373 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1376 		atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3253 	u16 phy_data;
3299 		phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3303 			phy_data =
3308 			phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3311 			phy_data =
3316 			phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3320 	atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3598 		u16 phy_data;
3603 			phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3607 				phy_data = MII_CR_FULL_DUPLEX |
3611 				phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3614 				phy_data = MII_CR_FULL_DUPLEX |
3619 				phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3622 		atl1_write_phy_reg(hw, MII_BMCR, phy_data);