Lines Matching refs:hw
39 #include "hw.h"
46 static int alx_wait_mdio_idle(struct alx_hw *hw)
52 val = alx_read_mem32(hw, ALX_MDIO);
61 static int alx_read_phy_core(struct alx_hw *hw, bool ext, u8 dev,
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ?
77 alx_write_mem32(hw, ALX_MDIO_EXTN, val);
88 alx_write_mem32(hw, ALX_MDIO, val);
90 err = alx_wait_mdio_idle(hw);
93 val = alx_read_mem32(hw, ALX_MDIO);
98 static int alx_write_phy_core(struct alx_hw *hw, bool ext, u8 dev,
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ?
111 alx_write_mem32(hw, ALX_MDIO_EXTN, val);
124 alx_write_mem32(hw, ALX_MDIO, val);
126 return alx_wait_mdio_idle(hw);
129 static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
131 return alx_read_phy_core(hw, false, 0, reg, phy_data);
134 static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
136 return alx_write_phy_core(hw, false, 0, reg, phy_data);
139 static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
141 return alx_read_phy_core(hw, true, dev, reg, pdata);
144 static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
146 return alx_write_phy_core(hw, true, dev, reg, data);
149 static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
153 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
157 return __alx_read_phy_reg(hw, ALX_MII_DBG_DATA, pdata);
160 static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
164 err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg);
168 return __alx_write_phy_reg(hw, ALX_MII_DBG_DATA, data);
171 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data)
175 spin_lock(&hw->mdio_lock);
176 err = __alx_read_phy_reg(hw, reg, phy_data);
177 spin_unlock(&hw->mdio_lock);
182 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data)
186 spin_lock(&hw->mdio_lock);
187 err = __alx_write_phy_reg(hw, reg, phy_data);
188 spin_unlock(&hw->mdio_lock);
193 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata)
197 spin_lock(&hw->mdio_lock);
198 err = __alx_read_phy_ext(hw, dev, reg, pdata);
199 spin_unlock(&hw->mdio_lock);
204 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data)
208 spin_lock(&hw->mdio_lock);
209 err = __alx_write_phy_ext(hw, dev, reg, data);
210 spin_unlock(&hw->mdio_lock);
215 static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata)
219 spin_lock(&hw->mdio_lock);
220 err = __alx_read_phy_dbg(hw, reg, pdata);
221 spin_unlock(&hw->mdio_lock);
226 static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data)
230 spin_lock(&hw->mdio_lock);
231 err = __alx_write_phy_dbg(hw, reg, data);
232 spin_unlock(&hw->mdio_lock);
237 static u16 alx_get_phy_config(struct alx_hw *hw)
242 val = alx_read_mem32(hw, ALX_PHY_CTRL);
247 val = alx_read_mem32(hw, ALX_DRV);
252 alx_read_phy_reg(hw, ALX_MII_DBG_ADDR, &phy_val);
259 static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val)
265 read = alx_read_mem32(hw, reg);
277 static bool alx_read_macaddr(struct alx_hw *hw, u8 *addr)
281 mac0 = alx_read_mem32(hw, ALX_STAD0);
282 mac1 = alx_read_mem32(hw, ALX_STAD1);
291 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr)
296 if (alx_read_macaddr(hw, addr))
300 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_STAT | ALX_SLD_START, &val))
302 alx_write_mem32(hw, ALX_SLD, val | ALX_SLD_START);
303 if (!alx_wait_reg(hw, ALX_SLD, ALX_SLD_START, NULL))
305 if (alx_read_macaddr(hw, addr))
309 val = alx_read_mem32(hw, ALX_EFLD);
311 if (!alx_wait_reg(hw, ALX_EFLD,
314 alx_write_mem32(hw, ALX_EFLD, val | ALX_EFLD_START);
315 if (!alx_wait_reg(hw, ALX_EFLD, ALX_EFLD_START, NULL))
317 if (alx_read_macaddr(hw, addr))
324 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr)
330 alx_write_mem32(hw, ALX_STAD0, val);
332 alx_write_mem32(hw, ALX_STAD1, val);
335 static void alx_reset_osc(struct alx_hw *hw, u8 rev)
339 /* clear Internal OSC settings, switching OSC by hw itself */
340 val = alx_read_mem32(hw, ALX_MISC3);
341 alx_write_mem32(hw, ALX_MISC3,
348 val = alx_read_mem32(hw, ALX_MISC);
356 alx_write_mem32(hw, ALX_MISC, val);
357 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
358 /* hw will automatically dis OSC after cab. */
359 val2 = alx_read_mem32(hw, ALX_MSIC2);
361 alx_write_mem32(hw, ALX_MSIC2, val2);
362 alx_write_mem32(hw, ALX_MSIC2, val2 | ALX_MSIC2_CALB_START);
369 alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
370 alx_write_mem32(hw, ALX_MISC, val);
376 static int alx_stop_mac(struct alx_hw *hw)
381 rxq = alx_read_mem32(hw, ALX_RXQ0);
382 alx_write_mem32(hw, ALX_RXQ0, rxq & ~ALX_RXQ0_EN);
383 txq = alx_read_mem32(hw, ALX_TXQ0);
384 alx_write_mem32(hw, ALX_TXQ0, txq & ~ALX_TXQ0_EN);
388 hw->rx_ctrl &= ~(ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
389 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
392 val = alx_read_mem32(hw, ALX_MAC_STS);
401 int alx_reset_mac(struct alx_hw *hw)
409 rev = alx_hw_revision(hw);
410 a_cr = alx_is_rev_a(rev) && alx_hw_with_cr(hw);
413 alx_write_mem32(hw, ALX_MSIX_MASK, 0xFFFFFFFF);
414 alx_write_mem32(hw, ALX_IMR, 0);
415 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
417 ret = alx_stop_mac(hw);
422 alx_write_mem32(hw, ALX_RFD_PIDX, 1);
426 pmctrl = alx_read_mem32(hw, ALX_PMCTRL);
428 alx_write_mem32(hw, ALX_PMCTRL,
434 val = alx_read_mem32(hw, ALX_MASTER);
435 alx_write_mem32(hw, ALX_MASTER,
441 val = alx_read_mem32(hw, ALX_RFD_PIDX);
447 val = alx_read_mem32(hw, ALX_MASTER);
457 alx_write_mem32(hw, ALX_MASTER, val | ALX_MASTER_PCLKSEL_SRDS);
460 alx_write_mem32(hw, ALX_PMCTRL, pmctrl);
463 alx_reset_osc(hw, rev);
465 /* clear Internal OSC settings, switching OSC by hw itself,
468 val = alx_read_mem32(hw, ALX_MISC3);
469 alx_write_mem32(hw, ALX_MISC3,
472 val = alx_read_mem32(hw, ALX_MISC);
476 alx_write_mem32(hw, ALX_MISC, val);
480 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
482 val = alx_read_mem32(hw, ALX_SERDES);
483 alx_write_mem32(hw, ALX_SERDES,
490 void alx_reset_phy(struct alx_hw *hw)
497 val = alx_read_mem32(hw, ALX_PHY_CTRL);
504 alx_write_mem32(hw, ALX_PHY_CTRL, val);
506 alx_write_mem32(hw, ALX_PHY_CTRL, val | ALX_PHY_CTRL_DSPRST_OUT);
512 alx_write_phy_dbg(hw, ALX_MIIDBG_LEGCYPS, ALX_LEGCYPS_DEF);
513 alx_write_phy_dbg(hw, ALX_MIIDBG_SYSMODCTRL,
515 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_VDRVBIAS,
519 val = alx_read_mem32(hw, ALX_LPI_CTRL);
520 alx_write_mem32(hw, ALX_LPI_CTRL, val & ~ALX_LPI_CTRL_EN);
521 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_LOCAL_EEEADV, 0);
524 alx_write_phy_dbg(hw, ALX_MIIDBG_TST10BTCFG, ALX_TST10BTCFG_DEF);
525 alx_write_phy_dbg(hw, ALX_MIIDBG_SRDSYSMOD, ALX_SRDSYSMOD_DEF);
526 alx_write_phy_dbg(hw, ALX_MIIDBG_TST100BTCFG, ALX_TST100BTCFG_DEF);
527 alx_write_phy_dbg(hw, ALX_MIIDBG_ANACTRL, ALX_ANACTRL_DEF);
528 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
529 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
532 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_NLP78,
534 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_S3DIG10,
537 if (hw->lnk_patch) {
539 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
541 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL3,
544 alx_read_phy_dbg(hw, ALX_MIIDBG_GREENCFG2, &phy_val);
545 alx_write_phy_dbg(hw, ALX_MIIDBG_GREENCFG2,
548 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
550 alx_write_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL5,
555 alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP | ALX_IER_LINK_DOWN);
560 void alx_reset_pcie(struct alx_hw *hw)
562 u8 rev = alx_hw_revision(hw);
567 pci_read_config_word(hw->pdev, PCI_COMMAND, &val16);
570 pci_write_config_word(hw->pdev, PCI_COMMAND, val16);
574 val = alx_read_mem32(hw, ALX_WOL0);
575 alx_write_mem32(hw, ALX_WOL0, 0);
577 val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
578 alx_write_mem32(hw, ALX_PDLL_TRNS1, val & ~ALX_PDLL_TRNS1_D3PLLOFF_EN);
581 val = alx_read_mem32(hw, ALX_UE_SVRT);
583 alx_write_mem32(hw, ALX_UE_SVRT, val);
586 val = alx_read_mem32(hw, ALX_MASTER);
587 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw)) {
590 alx_write_mem32(hw, ALX_MASTER,
596 alx_write_mem32(hw, ALX_MASTER,
602 alx_enable_aspm(hw, true, true);
607 void alx_start_mac(struct alx_hw *hw)
611 rxq = alx_read_mem32(hw, ALX_RXQ0);
612 alx_write_mem32(hw, ALX_RXQ0, rxq | ALX_RXQ0_EN);
613 txq = alx_read_mem32(hw, ALX_TXQ0);
614 alx_write_mem32(hw, ALX_TXQ0, txq | ALX_TXQ0_EN);
616 mac = hw->rx_ctrl;
617 if (hw->duplex == DUPLEX_FULL)
622 hw->link_speed == SPEED_1000 ? ALX_MAC_CTRL_SPEED_1000 :
625 hw->rx_ctrl = mac;
626 alx_write_mem32(hw, ALX_MAC_CTRL, mac);
629 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc)
632 hw->rx_ctrl |= ALX_MAC_CTRL_RXFC_EN;
634 hw->rx_ctrl &= ~ALX_MAC_CTRL_RXFC_EN;
637 hw->rx_ctrl |= ALX_MAC_CTRL_TXFC_EN;
639 hw->rx_ctrl &= ~ALX_MAC_CTRL_TXFC_EN;
641 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
644 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en)
647 u8 rev = alx_hw_revision(hw);
649 pmctrl = alx_read_mem32(hw, ALX_PMCTRL);
668 if (alx_is_rev_a(rev) && alx_hw_with_cr(hw))
676 alx_write_mem32(hw, ALX_PMCTRL, pmctrl);
680 static u32 ethadv_to_hw_cfg(struct alx_hw *hw, u32 ethadv_cfg)
722 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl)
728 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, 0);
729 val = alx_read_mem32(hw, ALX_DRV);
746 if (alx_hw_giga(hw))
751 if (alx_write_phy_reg(hw, MII_ADVERTISE, adv) ||
752 alx_write_phy_reg(hw, MII_CTRL1000, giga) ||
753 alx_write_phy_reg(hw, MII_BMCR, cr))
764 err = alx_write_phy_reg(hw, MII_BMCR, cr);
768 alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, ALX_PHY_INITED);
769 val |= ethadv_to_hw_cfg(hw, ethadv);
772 alx_write_mem32(hw, ALX_DRV, val);
778 void alx_post_phy_link(struct alx_hw *hw)
781 u8 revid = alx_hw_revision(hw);
788 if (hw->link_speed != SPEED_UNKNOWN) {
789 alx_read_phy_ext(hw, ALX_MIIEXT_PCS, ALX_MIIEXT_CLDCTRL6,
792 alx_read_phy_dbg(hw, ALX_MIIDBG_AGC, &phy_val);
795 if ((hw->link_speed == SPEED_1000 &&
798 (hw->link_speed == SPEED_100 &&
801 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
803 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
805 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
808 alx_write_phy_dbg(hw, ALX_MIIDBG_AZ_ANADECT,
810 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG,
812 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
817 if (adj_th && hw->lnk_patch) {
818 if (hw->link_speed == SPEED_100) {
819 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
821 } else if (hw->link_speed == SPEED_1000) {
826 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
830 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB,
835 alx_read_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
837 alx_write_phy_ext(hw, ALX_MIIEXT_ANEG, ALX_MIIEXT_AFE,
840 if (adj_th && hw->lnk_patch) {
841 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE16DB,
843 alx_read_phy_dbg(hw, ALX_MIIDBG_MSE20DB, &phy_val);
846 alx_write_phy_dbg(hw, ALX_MIIDBG_MSE20DB, phy_val);
851 bool alx_phy_configured(struct alx_hw *hw)
855 cfg = ethadv_to_hw_cfg(hw, hw->adv_cfg);
857 hw_cfg = alx_get_phy_config(hw);
865 int alx_read_phy_link(struct alx_hw *hw)
867 struct pci_dev *pdev = hw->pdev;
871 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
875 err = alx_read_phy_reg(hw, MII_BMSR, &bmsr);
880 hw->link_speed = SPEED_UNKNOWN;
881 hw->duplex = DUPLEX_UNKNOWN;
886 err = alx_read_phy_reg(hw, ALX_MII_GIGA_PSSR, &giga);
895 hw->link_speed = SPEED_1000;
898 hw->link_speed = SPEED_100;
901 hw->link_speed = SPEED_10;
907 hw->duplex = (giga & ALX_GIGA_PSSR_DPLX) ? DUPLEX_FULL : DUPLEX_HALF;
915 int alx_clear_phy_intr(struct alx_hw *hw)
920 return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
923 void alx_disable_rss(struct alx_hw *hw)
925 u32 ctrl = alx_read_mem32(hw, ALX_RXQ0);
928 alx_write_mem32(hw, ALX_RXQ0, ctrl);
931 void alx_configure_basic(struct alx_hw *hw)
935 u8 chip_rev = alx_hw_revision(hw);
937 alx_set_macaddr(hw, hw->mac_addr);
939 alx_write_mem32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL);
943 alx_write_mem32(hw, ALX_IDLE_DECISN_TIMER,
946 alx_write_mem32(hw, ALX_SMB_TIMER, hw->smb_timer * 500UL);
948 val = alx_read_mem32(hw, ALX_MASTER);
952 alx_write_mem32(hw, ALX_MASTER, val);
953 alx_write_mem32(hw, ALX_IRQ_MODU_TIMER,
954 (hw->imt >> 1) << ALX_IRQ_MODU_TIMER1_SHIFT);
956 alx_write_mem32(hw, ALX_INT_RETRIG, ALX_INT_RETRIG_TO);
958 alx_write_mem32(hw, ALX_TINT_TPD_THRSHLD, hw->ith_tpd);
959 alx_write_mem32(hw, ALX_TINT_TIMER, hw->imt);
961 raw_mtu = ALX_RAW_MTU(hw->mtu);
962 alx_write_mem32(hw, ALX_MTU, raw_mtu);
964 hw->rx_ctrl &= ~ALX_MAC_CTRL_FAST_PAUSE;
970 alx_write_mem32(hw, ALX_TXQ1, val | ALX_TXQ1_ERRLGPKT_DROP_EN);
972 max_payload = pcie_get_readrq(hw->pdev) >> 8;
978 pcie_set_readrq(hw->pdev, 128 << ALX_DEV_CTRL_MAXRRS_MIN);
984 alx_write_mem32(hw, ALX_TXQ0, val);
989 alx_write_mem32(hw, ALX_HQTPD, val);
992 val = alx_read_mem32(hw, ALX_SRAM5);
1001 alx_write_mem32(hw, ALX_RXQ2,
1010 if (alx_hw_giga(hw))
1014 alx_write_mem32(hw, ALX_RXQ0, val);
1016 val = alx_read_mem32(hw, ALX_DMA);
1022 (hw->dma_chnl - 1) << ALX_DMA_RCHNL_SEL_SHIFT;
1023 alx_write_mem32(hw, ALX_DMA, val);
1031 alx_write_mem32(hw, ALX_WRR, val);
1034 void alx_mask_msix(struct alx_hw *hw, int index, bool mask)
1043 alx_write_mem32(hw, reg, val);
1044 alx_post_write(hw);
1048 bool alx_get_phy_info(struct alx_hw *hw)
1052 if (alx_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id[0]) ||
1053 alx_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id[1]))
1060 if (alx_read_phy_ext(hw, 3, MDIO_DEVS1, &devs1) ||
1061 alx_read_phy_ext(hw, 3, MDIO_DEVS2, &devs2))
1063 hw->mdio.mmds = devs1 | devs2 << 16;
1068 void alx_update_hw_stats(struct alx_hw *hw)
1071 hw->stats.rx_ok += alx_read_mem32(hw, ALX_MIB_RX_OK);
1072 hw->stats.rx_bcast += alx_read_mem32(hw, ALX_MIB_RX_BCAST);
1073 hw->stats.rx_mcast += alx_read_mem32(hw, ALX_MIB_RX_MCAST);
1074 hw->stats.rx_pause += alx_read_mem32(hw, ALX_MIB_RX_PAUSE);
1075 hw->stats.rx_ctrl += alx_read_mem32(hw, ALX_MIB_RX_CTRL);
1076 hw->stats.rx_fcs_err += alx_read_mem32(hw, ALX_MIB_RX_FCS_ERR);
1077 hw->stats.rx_len_err += alx_read_mem32(hw, ALX_MIB_RX_LEN_ERR);
1078 hw->stats.rx_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BYTE_CNT);
1079 hw->stats.rx_runt += alx_read_mem32(hw, ALX_MIB_RX_RUNT);
1080 hw->stats.rx_frag += alx_read_mem32(hw, ALX_MIB_RX_FRAG);
1081 hw->stats.rx_sz_64B += alx_read_mem32(hw, ALX_MIB_RX_SZ_64B);
1082 hw->stats.rx_sz_127B += alx_read_mem32(hw, ALX_MIB_RX_SZ_127B);
1083 hw->stats.rx_sz_255B += alx_read_mem32(hw, ALX_MIB_RX_SZ_255B);
1084 hw->stats.rx_sz_511B += alx_read_mem32(hw, ALX_MIB_RX_SZ_511B);
1085 hw->stats.rx_sz_1023B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1023B);
1086 hw->stats.rx_sz_1518B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1518B);
1087 hw->stats.rx_sz_max += alx_read_mem32(hw, ALX_MIB_RX_SZ_MAX);
1088 hw->stats.rx_ov_sz += alx_read_mem32(hw, ALX_MIB_RX_OV_SZ);
1089 hw->stats.rx_ov_rxf += alx_read_mem32(hw, ALX_MIB_RX_OV_RXF);
1090 hw->stats.rx_ov_rrd += alx_read_mem32(hw, ALX_MIB_RX_OV_RRD);
1091 hw->stats.rx_align_err += alx_read_mem32(hw, ALX_MIB_RX_ALIGN_ERR);
1092 hw->stats.rx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BCCNT);
1093 hw->stats.rx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_MCCNT);
1094 hw->stats.rx_err_addr += alx_read_mem32(hw, ALX_MIB_RX_ERRADDR);
1097 hw->stats.tx_ok += alx_read_mem32(hw, ALX_MIB_TX_OK);
1098 hw->stats.tx_bcast += alx_read_mem32(hw, ALX_MIB_TX_BCAST);
1099 hw->stats.tx_mcast += alx_read_mem32(hw, ALX_MIB_TX_MCAST);
1100 hw->stats.tx_pause += alx_read_mem32(hw, ALX_MIB_TX_PAUSE);
1101 hw->stats.tx_exc_defer += alx_read_mem32(hw, ALX_MIB_TX_EXC_DEFER);
1102 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL);
1103 hw->stats.tx_defer += alx_read_mem32(hw, ALX_MIB_TX_DEFER);
1104 hw->stats.tx_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BYTE_CNT);
1105 hw->stats.tx_sz_64B += alx_read_mem32(hw, ALX_MIB_TX_SZ_64B);
1106 hw->stats.tx_sz_127B += alx_read_mem32(hw, ALX_MIB_TX_SZ_127B);
1107 hw->stats.tx_sz_255B += alx_read_mem32(hw, ALX_MIB_TX_SZ_255B);
1108 hw->stats.tx_sz_511B += alx_read_mem32(hw, ALX_MIB_TX_SZ_511B);
1109 hw->stats.tx_sz_1023B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1023B);
1110 hw->stats.tx_sz_1518B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1518B);
1111 hw->stats.tx_sz_max += alx_read_mem32(hw, ALX_MIB_TX_SZ_MAX);
1112 hw->stats.tx_single_col += alx_read_mem32(hw, ALX_MIB_TX_SINGLE_COL);
1113 hw->stats.tx_multi_col += alx_read_mem32(hw, ALX_MIB_TX_MULTI_COL);
1114 hw->stats.tx_late_col += alx_read_mem32(hw, ALX_MIB_TX_LATE_COL);
1115 hw->stats.tx_abort_col += alx_read_mem32(hw, ALX_MIB_TX_ABORT_COL);
1116 hw->stats.tx_underrun += alx_read_mem32(hw, ALX_MIB_TX_UNDERRUN);
1117 hw->stats.tx_trd_eop += alx_read_mem32(hw, ALX_MIB_TX_TRD_EOP);
1118 hw->stats.tx_len_err += alx_read_mem32(hw, ALX_MIB_TX_LEN_ERR);
1119 hw->stats.tx_trunc += alx_read_mem32(hw, ALX_MIB_TX_TRUNC);
1120 hw->stats.tx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BCCNT);
1121 hw->stats.tx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_MCCNT);
1123 hw->stats.update += alx_read_mem32(hw, ALX_MIB_UPDATE);