apm/xgene/xgene_enet_hw.c

13 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
15 	u32 *ring_cfg = ring->state;
16 	u64 addr = ring->dma;
17 	enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
33 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
35 	u32 *ring_cfg = ring->state;
39 	is_bufpool = xgene_enet_is_bufpool(ring->id);
50 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
52 	u32 *ring_cfg = ring->state;
60 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
63 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
68 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
71 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
76 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
78 	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
81 	xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
83 		xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
84 				     ring->state[i]);
88 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
90 	memset(ring->state, 0, sizeof(ring->state));
91 	xgene_enet_write_ring_state(ring);
94 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
96 	xgene_enet_ring_set_type(ring);
98 	if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
99 	    xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
100 		xgene_enet_ring_set_recombbuf(ring);
102 	xgene_enet_ring_init(ring);
103 	xgene_enet_write_ring_state(ring);
106 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
111 	is_bufpool = xgene_enet_is_bufpool(ring->id);
113 	ring_id_val = ring->id & GENMASK(9, 0);
116 	ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
121 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
122 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
125 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
129 	ring_id = ring->id | OVERWRITE;
130 	xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
131 	xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
135 				    struct xgene_enet_desc_ring *ring)
137 	u32 size = ring->size;
141 	xgene_enet_clr_ring_state(ring);
142 	xgene_enet_set_ring_state(ring);
143 	xgene_enet_set_ring_id(ring);
145 	ring->slots = xgene_enet_get_numslots(ring->id, size);
147 	is_bufpool = xgene_enet_is_bufpool(ring->id);
148 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
149 		return ring;
151 	for (i = 0; i < ring->slots; i++)
152 		xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
154 	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
155 	data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
156 	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
158 	return ring;
161 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
166 	is_bufpool = xgene_enet_is_bufpool(ring->id);
167 	if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
170 	xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
171 	data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
172 	xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
175 	xgene_enet_clr_desc_ring_id(ring);
176 	xgene_enet_clr_ring_state(ring);
179 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
181 	iowrite32(count, ring->cmd);
184 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
186 	u32 __iomem *cmd_base = ring->cmd_base;
195 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
200 		ring->rx_crc_errors++;
204 		ring->rx_errors++;
207 		ring->rx_frame_errors++;
210 		ring->rx_length_errors++;
213 		ring->rx_frame_errors++;
216 		ring->rx_fifo_errors++;
733 			     struct xgene_enet_desc_ring *ring)
737 	if (xgene_enet_is_bufpool(ring->id)) {
739 		data = BIT(xgene_enet_get_fpsel(ring->id));
742 		data = BIT(xgene_enet_ring_bufnum(ring->id));