amd/xgbe/xgbe-phy-v1.c

222 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
224 		XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
227 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
229 		XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
232 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
234 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
235 	struct xgbe_phy_data *phy_data = pdata->phy_data;
243 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
244 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
250 	if (pdata->phy.pause_autoneg) {
252 		pdata->phy.tx_pause = 0;
253 		pdata->phy.rx_pause = 0;
256 			pdata->phy.tx_pause = 1;
257 			pdata->phy.rx_pause = 1;
260 				pdata->phy.rx_pause = 1;
262 				pdata->phy.tx_pause = 1;
267 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
268 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
291 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
292 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
299 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
302 	struct ethtool_link_ksettings *slks = &pdata->phy.lks;
307 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
313 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
318 static void xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata)
322 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
325 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
330 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
333 static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
336 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
339 static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
345 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
352 		status = XSIR0_IOREAD(pdata, SIR0_STATUS);
358 	netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",
363 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
364 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
367 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
369 	struct xgbe_phy_data *phy_data = pdata->phy_data;
373 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
376 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
378 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
381 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
383 	xgbe_phy_pcs_power_cycle(pdata);
386 	xgbe_phy_start_ratechange(pdata);
388 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
389 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
390 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
392 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
394 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
396 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
398 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
400 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
402 	XRXTX_IOWRITE(pdata, RXTX_REG22,
405 	xgbe_phy_complete_ratechange(pdata);
407 	netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
410 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
412 	struct xgbe_phy_data *phy_data = pdata->phy_data;
416 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
419 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
421 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
424 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
426 	xgbe_phy_pcs_power_cycle(pdata);
429 	xgbe_phy_start_ratechange(pdata);
431 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
432 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
433 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
435 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
437 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
439 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
441 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
443 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
445 	XRXTX_IOWRITE(pdata, RXTX_REG22,
448 	xgbe_phy_complete_ratechange(pdata);
450 	netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
453 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
455 	struct xgbe_phy_data *phy_data = pdata->phy_data;
459 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
462 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
464 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
467 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
469 	xgbe_phy_pcs_power_cycle(pdata);
472 	xgbe_phy_start_ratechange(pdata);
474 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
475 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
476 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
478 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
480 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
482 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
484 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
486 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
488 	XRXTX_IOWRITE(pdata, RXTX_REG22,
491 	xgbe_phy_complete_ratechange(pdata);
493 	netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
496 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
498 	struct xgbe_phy_data *phy_data = pdata->phy_data;
502 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
517 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
519 	struct xgbe_phy_data *phy_data = pdata->phy_data;
523 	if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) {
535 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
538 	struct xgbe_phy_data *phy_data = pdata->phy_data;
554 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
558 		xgbe_phy_kx_1000_mode(pdata);
561 		xgbe_phy_kx_2500_mode(pdata);
564 		xgbe_phy_kr_mode(pdata);
571 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
574 	if (pdata->phy.autoneg == AUTONEG_ENABLE) {
579 		cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
587 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
589 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
593 		return xgbe_phy_check_mode(pdata, mode,
596 		return xgbe_phy_check_mode(pdata, mode,
599 		return xgbe_phy_check_mode(pdata, mode,
606 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
608 	struct xgbe_phy_data *phy_data = pdata->phy_data;
626 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
635 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
636 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
641 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
646 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
652 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
657 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
659 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
664 		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
673 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
678 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
680 	struct ethtool_link_ksettings *lks = &pdata->phy.lks;
684 	phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
689 	ret = device_property_read_u32(pdata->phy_dev, XGBE_SPEEDSET_PROPERTY,
692 		dev_err(pdata->dev, "invalid %s property\n",
702 		dev_err(pdata->dev, "invalid %s property\n",
708 	if (device_property_present(pdata->phy_dev, XGBE_BLWC_PROPERTY)) {
709 		ret = device_property_read_u32_array(pdata->phy_dev,
714 			dev_err(pdata->dev, "invalid %s property\n",
723 	if (device_property_present(pdata->phy_dev, XGBE_CDR_RATE_PROPERTY)) {
724 		ret = device_property_read_u32_array(pdata->phy_dev,
729 			dev_err(pdata->dev, "invalid %s property\n",
738 	if (device_property_present(pdata->phy_dev, XGBE_PQ_SKEW_PROPERTY)) {
739 		ret = device_property_read_u32_array(pdata->phy_dev,
744 			dev_err(pdata->dev, "invalid %s property\n",
753 	if (device_property_present(pdata->phy_dev, XGBE_TX_AMP_PROPERTY)) {
754 		ret = device_property_read_u32_array(pdata->phy_dev,
759 			dev_err(pdata->dev, "invalid %s property\n",
768 	if (device_property_present(pdata->phy_dev, XGBE_DFE_CFG_PROPERTY)) {
769 		ret = device_property_read_u32_array(pdata->phy_dev,
774 			dev_err(pdata->dev, "invalid %s property\n",
783 	if (device_property_present(pdata->phy_dev, XGBE_DFE_ENA_PROPERTY)) {
784 		ret = device_property_read_u32_array(pdata->phy_dev,
789 			dev_err(pdata->dev, "invalid %s property\n",
814 	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
817 	pdata->phy_data = phy_data;