amd/xgbe/xgbe-dev.c

463 			      unsigned int queue)
468 		/* Does this queue handle the priority? */
469 		if (pdata->prio2q_map[prio] != queue)
531 	/* From MAC ver 30H the TFCR is per priority, instead of per queue */
2331 					      unsigned int queue,
2339 	if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2340 		/* PFC is active for this queue */
2355 			pdata->rx_rfa[queue] = 0;
2356 			pdata->rx_rfd[queue] = 0;
2362 			pdata->rx_rfa[queue] = 0;	/* Full - 1024 bytes */
2363 			pdata->rx_rfd[queue] = 1;	/* Full - 1536 bytes */
2369 			pdata->rx_rfa[queue] = 2;	/* Full - 2048 bytes */
2370 			pdata->rx_rfd[queue] = 5;	/* Full - 3584 bytes */
2391 	pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2392 	pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2444 	/* Calculate the fifo setting by dividing the queue's fifo size
2610 		   "%d Tx hardware queues, %d byte fifo per queue\n",
2621 	/* Clear any DCB related fifo/queue information */
2647 				   "RxQ%u, %u byte fifo queue\n", i,
2651 			   "%u Rx hardware queues, %u byte fifo per queue\n",
2659 	unsigned int qptc, qptc_extra, queue;
2671 	for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2674 				  "TXq%u mapped to TC%u\n", queue, i);
2675 			XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2677 			pdata->q2tc_map[queue++] = i;
2682 				  "TXq%u mapped to TC%u\n", queue, i);
2683 			XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2685 			pdata->q2tc_map[queue++] = i;
2722 	/* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2740 	unsigned int offset, queue, prio;
2749 	for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2750 		while ((queue < pdata->tx_q_count) &&
2751 		       (pdata->q2tc_map[queue] == i))
2752 			queue++;
2755 			  i, offset, queue - 1);
2756 		netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2757 		offset = queue;
3271 				     unsigned int queue)
3277 	 * packets. Wait for the Tx queue to empty the Tx fifo.  Don't
3282 		tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
3292 			    "timed out waiting for Tx queue %u to empty\n",
3293 			    queue);
3297 				 unsigned int queue)
3304 		return xgbe_txq_prepare_tx_stop(pdata, queue);
3307 	if (queue < DMA_DSRX_FIRST_QUEUE) {
3309 		tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
3311 		tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
3336 			    queue);
3351 	/* Enable each Tx queue */
3371 	/* Disable each Tx queue */
3385 				 unsigned int queue)
3391 	 * packets. Wait for the Rx queue to empty the Rx fifo.  Don't
3396 		rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3406 			    "timed out waiting for Rx queue %u to empty\n",
3407 			    queue);
3422 	/* Enable each Rx queue */
3449 	/* Disable each Rx queue */