amazon/ena/ena_com.c

810 	struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
812 		mmio_read->read_resp;
815 	u32 timeout = mmio_read->reg_read_to;
823 	if (!mmio_read->readless_supported)
826 	spin_lock_irqsave(&mmio_read->lock, flags);
827 	mmio_read->seq_num++;
829 	read_resp->req_id = mmio_read->seq_num + 0xDEAD;
832 	mmio_read_reg |= mmio_read->seq_num &
838 		if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
847 			   mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off);
859 	spin_unlock_irqrestore(&mmio_read->lock, flags);
1672 	struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1674 	spin_lock_init(&mmio_read->lock);
1675 	mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1676 						  &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1677 	if (unlikely(!mmio_read->read_resp))
1682 	mmio_read->read_resp->req_id = 0x0;
1683 	mmio_read->seq_num = 0x0;
1684 	mmio_read->readless_supported = true;
1695 	struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1697 	mmio_read->readless_supported = readless_supported;
1702 	struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1707 	dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp,
1708 			  mmio_read->read_resp_dma_addr);
1710 	mmio_read->read_resp = NULL;
1715 	struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1718 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1719 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);