amazon/ena/ena_com.c

131 	struct ena_com_aenq *aenq = &ena_dev->aenq;
135 	ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
137 	aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL);
139 	if (!aenq->entries) {
144 	aenq->head = aenq->q_depth;
145 	aenq->phase = 1;
147 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
148 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
154 	aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
165 	aenq->aenq_handlers = aenq_handlers;
1492 	u16 depth = ena_dev->aenq.q_depth;
1494 	WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1512 		dev_info(ena_dev->dmadev, "Can't get aenq configuration\n");
1516 	if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1518 			    "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1519 			    get_resp.u.aenq.supported_groups, groups_flag);
1529 	cmd.u.aenq.enabled_groups = groups_flag;
1632 	struct ena_com_aenq *aenq = &ena_dev->aenq;
1647 	size = ADMIN_AENQ_SIZE(aenq->q_depth);
1648 	if (ena_dev->aenq.entries)
1649 		dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr);
1650 	aenq->entries = NULL;
1943 	memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1944 	       sizeof(get_resp.u.aenq));
1988 	struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;
1997  * handles the aenq incoming events.
2004 	struct ena_com_aenq *aenq  = &ena_dev->aenq;
2010 	masked_head = aenq->head & (aenq->q_depth - 1);
2011 	phase = aenq->phase;
2012 	aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2037 		if (unlikely(masked_head == aenq->q_depth)) {
2041 		aenq_e = &aenq->entries[masked_head];
2045 	aenq->head += processed;
2046 	aenq->phase = phase;
2048 	/* Don't update aenq doorbell if there weren't any processed events */
2052 	/* write the aenq doorbell after all AENQ descriptors were read */
2054 	writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);