ethernet/agere/et131x.c

2801 	u32 *regs_buff = regs_data;
2812 	regs_buff[num++] = tmp;
2814 	regs_buff[num++] = tmp;
2816 	regs_buff[num++] = tmp;
2818 	regs_buff[num++] = tmp;
2820 	regs_buff[num++] = tmp;
2822 	regs_buff[num++] = tmp;
2824 	regs_buff[num++] = tmp;
2827 	regs_buff[num++] = tmp;
2830 	regs_buff[num++] = tmp;
2832 	regs_buff[num++] = tmp;
2834 	regs_buff[num++] = tmp;
2836 	regs_buff[num++] = tmp;
2838 	regs_buff[num++] = tmp;
2840 	regs_buff[num++] = tmp;
2842 	regs_buff[num++] = tmp;
2844 	regs_buff[num++] = tmp;
2847 	regs_buff[num++] = tmp;
2849 	regs_buff[num++] = tmp;
2851 	regs_buff[num++] = tmp;
2853 	regs_buff[num++] = tmp;
2855 	regs_buff[num++] = tmp;
2858 	regs_buff[num++] = tmp;
2860 	regs_buff[num++] = tmp;
2862 	regs_buff[num++] = tmp;
2864 	regs_buff[num++] = tmp;
2866 	regs_buff[num++] = tmp;
2868 	regs_buff[num++] = tmp;
2870 	regs_buff[num++] = tmp;
2872 	regs_buff[num++] = tmp;
2875 	regs_buff[num++] = readl(&aregs->global.txq_start_addr);
2876 	regs_buff[num++] = readl(&aregs->global.txq_end_addr);
2877 	regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
2878 	regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
2879 	regs_buff[num++] = readl(&aregs->global.pm_csr);
2880 	regs_buff[num++] = adapter->stats.interrupt_status;
2881 	regs_buff[num++] = readl(&aregs->global.int_mask);
2882 	regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
2883 	regs_buff[num++] = readl(&aregs->global.int_status_alias);
2884 	regs_buff[num++] = readl(&aregs->global.sw_reset);
2885 	regs_buff[num++] = readl(&aregs->global.slv_timer);
2886 	regs_buff[num++] = readl(&aregs->global.msi_config);
2887 	regs_buff[num++] = readl(&aregs->global.loopback);
2888 	regs_buff[num++] = readl(&aregs->global.watchdog_timer);
2891 	regs_buff[num++] = readl(&aregs->txdma.csr);
2892 	regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
2893 	regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
2894 	regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
2895 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
2896 	regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
2897 	regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
2898 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
2899 	regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
2900 	regs_buff[num++] = readl(&aregs->txdma.service_request);
2901 	regs_buff[num++] = readl(&aregs->txdma.service_complete);
2902 	regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
2903 	regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
2904 	regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
2905 	regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
2906 	regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
2907 	regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
2908 	regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
2909 	regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
2910 	regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
2911 	regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
2912 	regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
2913 	regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
2914 	regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
2915 	regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
2916 	regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
2919 	regs_buff[num++] = readl(&aregs->rxdma.csr);
2920 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
2921 	regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
2922 	regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
2923 	regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
2924 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
2925 	regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
2926 	regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
2927 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
2928 	regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
2929 	regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
2930 	regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
2931 	regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
2932 	regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
2933 	regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
2934 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
2935 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
2936 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
2937 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
2938 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
2939 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
2940 	regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
2941 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
2942 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
2943 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
2944 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
2945 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
2946 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
2947 	regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);