dsa/sja1105/sja1105_tas.c

88 	dev_dbg(ds->dev, "longest cycle time %lld ns\n", max_cycle_time);
101  * iterate cyclically through the "schedule". Each "cycle" has an entry point
103  * hardware calls each cycle a "subschedule".
105  * Subschedule (cycle) i starts when
123  *                 |cycle 0|cycle 1|
151  *  - cycle 0: iterates the schedule table from 0 to 2 (and back)
152  *  - cycle 1: iterates the schedule table from 3 to 5 (and back)
174 	int cycle = 0;
300 		schedule_entry_points[cycle].subschindx = cycle;
301 		schedule_entry_points[cycle].delta = entry_point_delta;
302 		schedule_entry_points[cycle].address = schedule_start_idx;
307 		for (i = cycle; i < 8; i++)
319 		cycle++;
336 		schedule_entry_points[cycle].subschindx = cycle;
337 		schedule_entry_points[cycle].delta = entry_point_delta;
338 		schedule_entry_points[cycle].address = schedule_start_idx;
340 		for (i = cycle; i < 8; i++)
371  * phase given by its cycle's @base_time plus its offset within the cycle
374  * - Collisions within one cycle's (actually the longest cycle's) time frame.
376  *   occurrence of each event within one cycle time.
377  * - Collisions in the future. Events may not collide within one cycle time,
378  *   but if two port schedules don't have the same periodicity (aka the cycle
400 	/* Check if the two cycle times are multiples of one another.
411 	 * the cycle time.
435 			 * first cycle time.
442 				 * within the first cycle time.
536 	/* The cycle time extension is the amount of time the last cycle from
541 	 * So don't add insult over injury and just say we don't support cycle
686  * up a delta, which is 200ns), and wrapping around at the end of each cycle.
707  * cycle times have to be multiples of one another anyway, this means the
708  * correction period can simply be the largest cycle time, hence the current
710  * cycle, and therefore predictable.
715  * your best-effort traffic at the beginning of a cycle, and your