dsa/sja1105/sja1105_main.c

194 		/* Disable learning and I/O on user ports by default -
223 	list_for_each_entry(dp, &ds->dst->ports, list) {
230 		 * enabled for the DSA ports. CPU ports use software-assisted
233 		 * CPU ports in a cross-chip topology if multiple CPU ports
240 		 * CPU and DSA ports.
457  * All DT-defined ports are members of this VLAN, and there are no
547 	/* Then manage the forwarding domain for user ports. These can forward
566 	/* Then manage the forwarding domain for DSA links and CPU ports (the
615 	/* Finally, manage the egress flooding domain. All ports start up with
740  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
799 	 * and mac_fltres0 on all ports except itself. Default to an invalid
811 	 * on SJA1110 which support multiple cascaded ports, this field is a
821 		/* Upstream ports can be dedicated CPU ports or
835 		/* Cascade ports are downstream-facing DSA links */
1126  * back to the legacy behavior and apply delays on fixed-link ports based on
1252 	ports_node = of_get_child_by_name(switch_node, "ports");
1254 		ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1256 		dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1414 		/* Changing the PHY mode on SERDES ports is possible and makes
1990  * enable flooding towards this port from all ingress ports that are in the
2042 		 * other ports in the same bridge, and viceversa.
2046 		/* For the ports already under the bridge, only one thing needs
2050 		 * that is new to the bridge), we need to add all other ports
2053 		 * the domain contains all other bridge ports.
2590 	/* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2664 		list_for_each_entry(dp, &dst->ports, list) {
2846  * mirroring on all other (@from) ports.