dsa/microchip/lan937x_main.c

36 	int ret;
39 	ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
40 	if (ret < 0)
41 		return ret;
43 	ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
44 	if (ret < 0)
45 		return ret;
68 	int ret;
74 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
75 	if (ret < 0)
76 		return ret;
79 	ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
80 	if (ret < 0)
81 		return ret;
84 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
86 	if (ret < 0)
87 		return ret;
89 	ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
92 	if (ret < 0) {
94 		return ret;
104 	int ret;
110 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
111 	if (ret < 0)
112 		return ret;
115 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
116 	if (ret < 0)
117 		return ret;
119 	ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
122 	if (ret < 0) {
124 		return ret;
144 	int ret;
147 	ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
148 	if (ret < 0)
149 		return ret;
152 	ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
153 	if (ret < 0)
154 		return ret;
157 	ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
158 	if (ret < 0)
159 		return ret;
161 	ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT);
162 	if (ret < 0)
163 		return ret;
165 	ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
166 	if (ret < 0)
167 		return ret;
230 	int ret;
238 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
241 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
243 	if (ret < 0) {
245 		return ret;
249 	ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
250 	if (ret) {
252 		return ret;
262 	int ret;
266 	ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value);
267 	if (ret < 0)
268 		return ret;
358 	int ret;
361 	ret = lan937x_enable_spi_indirect_access(dev);
362 	if (ret < 0) {
364 		return ret;