dsa/microchip/lan937x_main.c

21 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
23 	return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
26 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
29 	return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
33 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
39 	ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
43 	ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
50 	return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
53 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
61 	return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
64 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
71 	if (!dev->info->internal_phy[addr])
74 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
79 	ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
84 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
89 	ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
93 		dev_err(dev->dev, "Failed to write phy register\n");
100 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
107 	if (!dev->info->internal_phy[addr])
110 	ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
115 	ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
119 	ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2,
123 		dev_err(dev->dev, "Failed to read phy register\n");
128 	return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
131 int lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
133 	return lan937x_internal_phy_read(dev, addr, reg, data);
136 int lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
138 	return lan937x_internal_phy_write(dev, addr, reg, val);
141 int lan937x_reset_switch(struct ksz_device *dev)
147 	ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
152 	ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
157 	ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
161 	ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT);
165 	ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
169 	return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
172 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
174 	const u32 *masks = dev->info->masks;
175 	const u16 *regs = dev->info->regs;
176 	struct dsa_switch *ds = dev->ds;
181 		lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
185 	ksz9477_port_queue_split(dev, port);
188 	lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
192 	lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
194 	if (!dev->info->internal_phy[port])
195 		lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
205 	dev->dev_ops->cfg_port_member(dev, port, member);
210 	struct ksz_device *dev = ds->priv;
214 		if (dev->info->cpu_ports & (1 << dp->index)) {
215 			dev->cpu_port = dp->index;
218 			lan937x_port_setup(dev, dp->index, true);
227 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
229 	struct dsa_switch *ds = dev->ds;
238 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
241 		ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
244 		dev_err(ds->dev, "failed to enable jumbo\n");
249 	ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
251 		dev_err(ds->dev, "failed to update mtu for port %d\n", port);
258 int lan937x_set_ageing_time(struct ksz_device *dev, unsigned int msecs)
266 	ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value);
272 	return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value);
275 static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
280 	ksz_pread16(dev, port, reg, &data16);
284 	ksz_pwrite16(dev, port, reg, data16);
288 	ksz_pwrite16(dev, port, reg, data16);
291 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
301 	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
304 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
311 	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
314 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
319 	if (dev->info->supports_rgmii[port]) {
326 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port)
328 	struct ksz_port *p = &dev->ports[port];
331 		lan937x_set_rgmii_tx_delay(dev, port);
332 		dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
337 		lan937x_set_rgmii_rx_delay(dev, port);
338 		dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
343 int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val)
345 	return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val);
348 int lan937x_switch_init(struct ksz_device *dev)
350 	dev->port_mask = (1 << dev->info->port_cnt) - 1;
357 	struct ksz_device *dev = ds->priv;
361 	ret = lan937x_enable_spi_indirect_access(dev);
363 		dev_err(dev->dev, "failed to enable spi indirect access");
373 	lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
380 	lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
383 	lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
386 	lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
397 void lan937x_switch_exit(struct ksz_device *dev)
399 	lan937x_reset_switch(dev);