net/can/xilinx_can.c

221  * @write_reg:			For writing data to CAN registers
247 	void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
455 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
511 	priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
512 	priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
536 		priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0);
537 		priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1);
591 	priv->write_reg(priv, XCAN_IER_OFFSET, ier);
603 		priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001);
605 	priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
606 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
701 	priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id);
705 	priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc);
711 			priv->write_reg(priv, ramoff,
722 			priv->write_reg(priv,
728 			priv->write_reg(priv,
758 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK);
791 	priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX));
1096 	priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
1102 		priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
1202 		priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK |
1292 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK);
1352 			priv->write_reg(priv, XCAN_FSR_OFFSET,
1358 			priv->write_reg(priv, XCAN_ICR_OFFSET,
1369 			priv->write_reg(priv, XCAN_IER_OFFSET, ier);
1401 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
1424 			priv->write_reg(priv, XCAN_ICR_OFFSET,
1435 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
1478 		priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
1497 		priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors);
1505 		priv->write_reg(priv, XCAN_IER_OFFSET, ier);
2030 	priv->write_reg = xcan_write_reg_le;
2042 		priv->write_reg = xcan_write_reg_be;
2060 		priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000);
2061 		priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000);
2070 		priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK |