Lines Matching defs:sdr
895 const struct nand_sdr_timings *sdr;
898 sdr = nand_get_sdr_timings(conf);
899 if (IS_ERR(sdr))
900 return PTR_ERR(sdr);
902 if (sdr->tRP_min != sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
911 TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
912 TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
914 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
915 TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
916 TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
917 TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
919 TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
920 TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
921 TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
923 cyc = sdr->tDS_min + sdr->tDH_min;
924 cle = sdr->tCLH_min + sdr->tCLS_min;
925 ale = sdr->tALH_min + sdr->tALS_min;
926 bef_dly = sdr->tWB_max - sdr->tDH_min;
927 ca_to_data = sdr->tWHR_min + sdr->tREA_max - sdr->tDH_min;
960 TIM_GEN_SEQ2_D8(TO_CYCLES64(sdr->tRR_min + sdr->tREA_max, period_ns)) |
961 TIM_GEN_SEQ2_D9(TO_CYCLES64(sdr->tRR_min, period_ns)) |
967 TIM_GEN_SEQ3_D12(TO_CYCLES64(sdr->tCLH_min - sdr->tDH_min, period_ns));