Lines Matching refs:ctlreg
324 dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
328 dev->ctlreg |= R852_CTL_DATA;
331 dev->ctlreg |= R852_CTL_COMMAND;
334 dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
336 dev->ctlreg &= ~R852_CTL_WRITE;
340 dev->ctlreg |= R852_CTL_WRITE;
342 r852_write_reg(dev, R852_CTL, dev->ctlreg);
347 if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
348 dev->ctlreg |= R852_CTL_WRITE;
349 r852_write_reg(dev, R852_CTL, dev->ctlreg);
409 dev->ctlreg |= R852_CTL_ECC_ENABLE;
413 dev->ctlreg | R852_CTL_ECC_ACCESS);
416 r852_write_reg(dev, R852_CTL, dev->ctlreg);
421 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
422 r852_write_reg(dev, R852_CTL, dev->ctlreg);
440 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
441 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
454 r852_write_reg(dev, R852_CTL, dev->ctlreg);
479 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
481 r852_write_reg(dev, R852_CTL, dev->ctlreg);
1018 if (dev->ctlreg & R852_CTL_CARDENABLE)