nand/raw/pl35x-nand-controller.c

3  * ARM PL35X NAND flash controller driver
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
33 /* SMC controller status register (RO) */
126  * struct pl35x_nandc - NAND flash controller driver structure
130  * @controller: Core NAND controller structure
132  * @selected_chip: NAND chip currently selected by the controller
140 	struct nand_controller controller;
149 	return container_of(ctrl, struct pl35x_nandc, controller);
248 			"Timeout polling on NAND controller interrupt (0x%x)\n",
266 			"Timeout polling on ECC controller interrupt\n");
297 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
315 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
335 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
367 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
506 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
585  * There is a limitation with SMC controller: ECC_LAST must be set on the
597 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
665 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
787 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
806 	 * expressed in NAND controller clock cycles. We use the TO_CYCLE()
943 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);
1015 	/* Ensure the ECC controller is bypassed by default */
1069 	chip->controller = &nfc->controller;
1148 	nand_controller_init(&nfc->controller);
1149 	nfc->controller.ops = &pl35x_nandc_ops;
1198 MODULE_DESCRIPTION("ARM PL35X NAND controller driver");