Lines Matching defs:in
309 dev_err(nfc->dev, "Error in Buswidth\n");
331 static void pl35x_nand_read_data_op(struct nand_chip *chip, u8 *in,
339 u32 *buf32 = (u32 *)in;
340 u8 *buf8 = (u8 *)in;
419 /* One error in the main data; to be corrected */
431 /* One error in the ECC data; no action needed */
545 /* Copy the HW calculated ECC bytes in the OOB buffer */
630 /* Wait the data to be available in the NAND cache */
745 pl35x_nand_read_data_op(chip, data_instr->ctx.data.buf.in,
805 * SDR timings are given in pico-seconds while NFC timings must be
806 * expressed in NAND controller clock cycles. We use the TO_CYCLE()
812 * PL35X SMC needs one extra read cycle in SDR Mode 5. This is not
813 * written anywhere in the datasheet but is an empirical observation.